Current code does not call clk_prepare(phy->optclk) when using the old
usb_otg_ss_refclk960m name. Fix it.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Remove extra space in MODULE_ALIAS.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Acked-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

When phy_pm_runtime_get_sync() returns -ENOTSUPP, phy_exit() also returns
-ENOTSUPP if !phy->ops->exit. Fix it.
Also move the code to override ret close to the code we got ret.
I think it is less error prone this way.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Acked-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Prefer devm_kcalloc over devm_kzalloc with multiply.
In additional, use sizeof(phy) is incorrect, fix it.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Acked-by: Gabriel Fernandez<gabriel.fernandez@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Prefer devm_kcalloc over devm_kzalloc with multiply.
In additional, use sizeof(phy) is incorrect, fix it.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Acked-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

It's pointless to set twl->linkstat twice.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Current code uses args->args[0] as array subscript of phy_drd->phys[].
So the valid value range for args->args[0] is 0 ... EXYNOS5_DRDPHYS_NUM - 1.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Reviewed by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

devm_phy_create() stores the pointer to the new PHY at the address
returned by devres_alloc(). The res parameter passed to devm_phy_match()
is therefore the location where the pointer to the PHY is stored, hence
it needs to be dereferenced before comparing to the match data in order
to find the correct match.

Cc: <stable@vger.kernel.org> # v3.13+
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

If rockchip_usb_phy_power() fails, we need to call clk_disable_unprepare()
before return. This is to ensure we have balanced clk_enable/disable calls.
Also remove unneeded ret checking in rockchip_usb_phy_power_off.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Code simplification. No functional change.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Acked-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Current code uses num_phys settings to tell the number of entries in phys.
Thus remove the NULL terminating entry from phys array which is not necessary.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This prevent NULL pointer dereference if res is NULL.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Acked-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

If IS_ERR(state->regs) the .probe fails.
So IS_ERR(state->regs) test in exynos_dp_video_phy_pwr_isol() is not necessary.
exynos_dp_video_phy_pwr_isol() simply does a regmap_update_bits() call now,
just call regmap_update_bits() instead and return proper return value.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The state->regmap is initialized by devm_regmap_init_mmio().
So it's fine to use spin_lock rather than mutex to protct state->regmap rmw
operations.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
[Julia.Lawall@lip6.fr: Found an issue with the original patch w.r.t unbalanced
 spin_lock call]
Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

syscon_regmap_lookup_by_phandle() returns ERR_PTR on error.
Thus don't use null test against state->regmap.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add missing .owner field in miphy28lp_ops, which is used for refcounting.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Set it once is enough and it's done after devm_kzalloc().
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

At the context we have pointer to struct phy, it's useful to call
phy_get_drvdata() to get the address of cluster_phy. This has slightly
better readability than calling dev_get_drvdata(phy->dev.parent).
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Currently, of_get_child_count() is called in each iteration of the for loop in
miphy365x_xlate(). This patch stores the return value of of_get_child_count()
in miphy_dev->nphys and call of_get_child_count() once in miphy365x_probe().
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Currently, of_get_child_count() is called in each iteration of the for loop in
miphy28lp_xlate(). This patch stores the return value of of_get_child_count()
in miphy_dev->nphys and call of_get_child_count() once in miphy28lp_probe().
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
update the miphy365 phy driver to access sysconfig register offsets via
syscfg dt property.

This is because the reg property should not be mixing address spaces
like it does currently for miphy365. This change then also aligns us
to how other platforms such as keystone and bcm7445 pass there syscon
offsets via DT.

This patch breaks DT compatibility, but this platform is considered WIP,
and is only used by a few developers who are upstreaming support for it.
This change has been done as a single atomic commit to ensure it is
bisectable.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NMaxime Coquelin <maxime.coquelin@st.com>
Tested-by: NMaxime Coquelin <maxime.coquelin@st.com>

After the Exynos Power Management Unit (PMU) driver was converted
to the platform device driver in commit 14fc8b93
("ARM: EXYNOS: Add platform driver support for Exynos PMU") and
then PMU device nodes added to Exynos4 DTs in commit
7b9613ac ("ARM: dts: add PMU syscon node for exynos4")
the mipi video phy driver started failing probing, due to overlapping
memory mapped register region resources.

Now all the Exynos peripheral devices which have registers in the PMU
region are supposed to use the regmap provided by the syscon driver.
So support for regmap is added in this patch, this unfortunately
creates yet another indirection into that supposedly trivial driver.

The additional mutex is required because single register is used by
PHY pairs (they share bit in a register). An improvement here could
be to allow a PHY instance be created with a driver custom mutex,
which would then be common for each PHY pair. This would eliminate
one of 3 mutexes which need to be taken in the phy_power_on/
phy_power_off code path. However, I tried to keep this bug fix patch
possibly simple.

This change is needed to make MIPI DSI displays and MIPI CSI-2
camera sensors working again on Exynos4 boards.

Cc: Pankaj Dubey <pankaj.dubey@samsung.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
currently this driver can support RK3288. The RK3288 SoC have
three independent USB PHY IPs which are all configured through a
set of registers located in the GRF (general register files)
module.
Signed-off-by: NYunzhi Li <lyz@rock-chips.com>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
update the phy driver to not use the reg property to access the sysconfig
register offsets.

This is because other phy's (miphy28, miphy365) have a combination of
memory mapped registers and sysconfig control regs, and we shouldn't
be mixing address spaces in the reg property. In addition we would
ideally like the sysconfig offsets to be passed via DT in a uniform way.

This new method will also allow us to support devices which have sysconfig
registers in different banks more easily and it is also analagous to how
keystone and bcm7745 platforms pass there syscon offsets in DT.

This breaks DT compatibility, but this platform is considered WIP, and
is only used by a few developers who are upstreaming support for it.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
update the miphy28lp phy driver to access sysconfig register offsets via
syscfg dt property.

This is because the reg property should not be mixing address spaces like
it does currently for miphy28lp. This change then also aligns us to how other
platforms such as keystone and bcm7445 pass there syscon offsets via DT.

I have updated the miphy28lp phy driver same way as Peter's implementation.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

In case of error, the function devm_ioremap_resource() returns
ERR_PTR() and never returns NULL. The NULL test in the return
value check should be replaced with IS_ERR().
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Failed test case: Boot without SATA drive connected. Suspend/resume
the board and then connect SATA drive. It fails to enumerate.

Due to Errata i783 "SATA Lockup After SATA DPLL Unlock/Relock"
we can't allow SATA DPLL to be in the unlocked state.
The SATA refclk (sata_ref_clk) is the source of the SATA_DPLL.
This clock is being controlled only by the AHCI SATA driver and is
shut off during system suspend (if the SATA drive was not already attached)
causing the SATA DPLL to be unlocked and so causing errata i783.

To prevent sata_ref_clk from being disabled, we add the control of
this clock to the SATA PHY driver and prevent it from being disabled.

This also fixes the issue of SATA not working on OMAP5/DRA7 when
AHCI platform driver is built as a module.

NOTE: Device tree changes also required for OMAP5 & DRA7.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

On system suspend, the runtime_suspend() driver hook doesn't get
called for USB phy and so the clocks are not disabled in the driver.
This causes the L3INIT_960M_GFCLK and L3INIT_480M_GFCLK to remain
active on the DRA7 platform while in system suspend.

In case of pcie-phy, the runtime_suspend hook gets called after
the suspend hook so we introduce a flag phy->enabled to keep
track if our clocks are enabled or not to prevent multiple
enable/disables.

Add suspend/resume hooks to the driver.
Move enabling/disabling clock code into helper functions.
Reported-by: NNishant Menon <nm@ti.com>
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This change adds a support for a 14nm qcom-ufs phy that is
required in platforms that use ufs-qcom controller.
Signed-off-by: NYaniv Gardi <ygardi@codeaurora.org>
Reviewed-by: NDov Levenglick <dovl@codeaurora.org>
Signed-off-by: NChristoph Hellwig <hch@lst.de>

This change adds a support for a 20nm qcom-ufs phy that is required in
platforms that use ufs-qcom controller.
Signed-off-by: NYaniv Gardi <ygardi@codeaurora.org>
Reviewed-by: NDov Levenglick <dovl@codeaurora.org>
Signed-off-by: NChristoph Hellwig <hch@lst.de>

This change adds a generic and common API support for ufs phy QUALCOMM
Technologies. This support provides common code and also points
to specific phy callbacks to differentiate between different behaviors
of frequent use-cases (like power on, power off, phy calibration etc).
Signed-off-by: NYaniv Gardi <ygardi@codeaurora.org>
Reviewed-by: NDov Levenglick <dovl@codeaurora.org>
Signed-off-by: NChristoph Hellwig <hch@lst.de>

Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
update the miphy365 phy driver to access sysconfig register offsets via
syscfg dt property.

This is because the reg property should not be mixing address spaces
like it does currently for miphy365. This change then also aligns us
to how other platforms such as keystone and bcm7445 pass there syscon
offsets via DT.

This patch breaks DT compatibility, but this platform is considered WIP,
and is only used by a few developers who are upstreaming support for it.
This change has been done as a single atomic commit to ensure it is
bisectable.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
update the phy driver to not use the reg property to access the sysconfig
register offsets.

This is because other phy's (miphy28, miphy365) have a combination of
memory mapped registers and sysconfig control regs, and we shouldn't
be mixing address spaces in the reg property. In addition we would
ideally like the sysconfig offsets to be passed via DT in a uniform way.

This new method will also allow us to support devices which have sysconfig
registers in different banks more easily and it is also analagous to how
keystone and bcm7745 platforms pass there syscon offsets in DT.

This breaks DT compatibility, but this platform is considered WIP, and
is only used by a few developers who are upstreaming support for it.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Prior to DRA74x silicon rev 1.1, pcie_pcs register bits 8-15 and bits 16-23
were used to configure RC delay count for phy1 and phy2 respectively.
phyid was used as index to distinguish the phys and to configure the delay
values appropriately.

As of DRA74x silicon rev 1.1, pcie_pcs register definition has changed.
Bits 16-23 are used to configure delay values for *both* phy1 and phy2.

Hence phyid is no longer required.

So, drop id field from ti_pipe3 structure and its subsequent references
for configuring pcie_pcs register.

Also, pcie_pcs register now needs to be configured with delay value of 0x96
at bit positions 16-23. See register description of CTRL_CORE_PCIE_PCS in
ARM572x TRM, SPRUHZ6, October 2014, section 18.5.2.2, table 18-1804.

This is needed to ensure Gen2 cards are enumerated consistently.

DRA72x silicon behaves same way as DRA74x rev 1.1 as far as this functionality
is considered.

Test results on DRA74x and DRA72x EVMs:

Before patch
------------
DRA74x ES 1.0: Gen1 cards work, Gen2 cards do not work (expected result due to
silicon errata)
DRA74x ES 1.1: Gen1 cards work, Gen2 cards do not work sometimes due to incorrect
programming of register

DRA72x: Gen1 cards work, Gen2 cards do not work sometimes due to incorrect
programming of register

After patch
-----------
DRA74x ES 1.0: Gen1 cards work, Gen2 cards do not work (expected result due to
silicon errata)
DRA74x ES 1.1: Gen1 cards work, Gen2 cards work consistently.

DRA72x: Gen1 and Gen2 cards enumerate consistently.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The allwinner SDK uses a value of 3 for the disconnect threshold setting on
sun6i, do the same in the kernel.

In my previous experience with sun5i problems getting the threshold right
is important to avoid usb2 devices being unplugged sometimes going unnoticed.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

We need to unlock before returning the -EINVAL here.
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Acked-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

After commit b2b49ccb (PM: Kconfig: Set PM_RUNTIME if PM_SLEEP is
selected) PM_RUNTIME is always set if PM is set, so #ifdef blocks
depending on CONFIG_PM_RUNTIME may now be changed to depend on
CONFIG_PM.

Replace CONFIG_PM_RUNTIME with CONFIG_PM everywhere under
drivers/phy/.
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: NKishon Vijay Abraham I <kishon@ti.com>

The Armada 375 SoC comes with an USB2 host and device controller and
an USB3 controller. The USB cluster control register allows to manage
common features of both USB controllers.

This commit adds a driver integrated in the generic PHY framework to
control this USB cluster feature.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
[ kishon@ti.com : Made it to use the updated devm_phy_create API and
		  soem cosmentic changes in Kconfig file.]
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Acked-by: NJason Cooper <jason@lakedaemon.net>

Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR

Generated by: coccinelle/api/ptr_ret.cocci
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This PHY controller is also present on Exynos7 platform
in arch-exynos family.
So PHY_EXYNOS5_USBDRD should now depend on ARCH_EXYNOS.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>