The register address should be the full address of the rng, not the
offset from the start of the SCU.

Fixes: 5daa8212 ("ARM: dts: aspeed: Describe random number device")
Reviewed-by: NAndrew Jeffery <andrew@aj.id.au>
Signed-off-by: NJoel Stanley <joel@jms.id.au>
Signed-off-by: NOlof Johansson <olof@lixom.net>

ENET "ipg" clock should be IMX7D_ENETx_IPG_ROOT_CLK
rather than IMX7D_ENET_AXI_ROOT_CLK which is for ENET bus
clock.

Based on Andy Duan's patch from the NXP kernel tree.
Signed-off-by: NAnson Huang <Anson.Huang@nxp.com>
Reviewed-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The clocks for the 3 MMC controllers on pxa3xx platforms are CLK_MMC1,
CLK_MMC2 and CLK_MMC3. CLK_MMC is only for pxa2xx.
Signed-off-by: NDaniel Mack <daniel@zonque.org>
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>

The PXA3xx series features some extended GPIO banks which are named GPIO0_2,
GPIO1_2 etc. The PXA300, PXA310 and PXA320 have different numbers of such
pins, and they also have variant-specific register offsets.
Signed-off-by: NDaniel Mack <daniel@zonque.org>
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>

The PXA GPIO driver calls out to the pinctrl driver for claiming pins
unless the config has CONFIG_PINCTRL unset. IOW, if a pinctrl driver is
active, it must be visible to the GPIO driver.
Signed-off-by: NDaniel Mack <daniel@zonque.org>
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>

Reviewed-by: NAbhishek Sahu <absahu@codeaurora.org>
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NSricharan R <sricharan@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Reviewed-by: NAbhishek Sahu <absahu@codeaurora.org>
Signed-off-by: NSricharan R <sricharan@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add the common data for all dk07 based boards.
Reviewed-by: NAbhishek Sahu <absahu@codeaurora.org>
Signed-off-by: NSricharan R <sricharan@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Reviewed-by: NAbhishek Sahu <absahu@codeaurora.org>
Signed-off-by: NSricharan R <sricharan@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Reviewed-by: NAbhishek Sahu <absahu@codeaurora.org>
Tested-by: NVaradarajan Narayanan <varada@codeaurora.org>
Signed-off-by: NSricharan R <sricharan@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add the common parts for the dk04 boards.
Reviewed-by: NAbhishek Sahu <absahu@codeaurora.org>
Signed-off-by: NSricharan R <sricharan@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

The max opp frequency is 716MHZ. So update that.
Reviewed-by: NAbhishek Sahu <absahu@codeaurora.org>
Signed-off-by: NSricharan R <sricharan@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.
Reviewed-by: NAbhishek Sahu <absahu@codeaurora.org>
Signed-off-by: NSricharan R <sricharan@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add a 'chosen' node to select the serial console.
This is needed when bootloaders do not pass the
'console=' bootargs.
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NSricharan R <sricharan@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

This patch adds a DTS file for Sony Xperia Z1 Compact with support for
regulators, serial UART, eMMC/SD-card, USB, charger, backlight,
coincell and buttons.

Work based on arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts.
Signed-off-by: NAttila Szöllősi <ata2001@airmail.cc>
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

This enables both USB ports as host with EHCI and UHCI
attached to them.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: NAndrew Jeffery <andrew@aj.id.au>
Signed-off-by: NJoel Stanley <joel@jms.id.au>

This adds the USB controllers to the DT template of the
AST24xx and AST25xx SoCs.

This patch doesn't enable them by default on any board specific
.dts yet. This will be done when we have the necessary clock/reset
and pinmux support. In the meantime though, this will work if
u-boot configures things properly.

For the AST2400 I only added pinmux definition for port 1
which is dual USB1/USB2. There are additional USB1 only ports
that might require more work but I don't have HW to test at
hand so I'm leaving that to whoever cares.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: NAndrew Jeffery <andrew@aj.id.au>
Signed-off-by: NJoel Stanley <joel@jms.id.au>

S2600WF is a Intel platform family with an ASPEED AST2500 BMC.
Signed-off-by: NJames Feist <james.feist@linux.intel.com>
Signed-off-by: NJoel Stanley <joel@jms.id.au>

The Inventec Lanyang is Power 9 platform with ast2500 BMC.
Signed-off-by: NBrian Yang <yang.brianc.w@inventec.com>
Acked-by: NAndrew Jeffery <andrew@aj.id.au>
Signed-off-by: NJoel Stanley <joel@jms.id.au>

Initial introduction of Portwell Neptune family equipped with
Aspeed 2500 BMC SoC. Neptune is a x86 server development kit with a
ASPEED ast2500 BMC manufactured by Portwell. Specifically, This
adds the neptune platform device tree file including the flash
layout used by the neptune machines.
Signed-off-by: NAmithash Prasad <amithash@fb.com>
Acked-by: NAndrew Jeffery <andrew@aj.id.au>
Signed-off-by: NJoel Stanley <joel@jms.id.au>

Set watchdog 2 to boot from the alternate flash chip when the watchdog
timer expires and the system is reset. This enables "brick protection."
Signed-off-by: NEddie James <eajames@linux.vnet.ibm.com>
Signed-off-by: NJoel Stanley <joel@jms.id.au>

Signed-off-by: NChristopher Bostic <cbostic@linux.vnet.ibm.com>
Signed-off-by: NJoel Stanley <joel@jms.id.au>

Enable gpio-keys events for the checkstop and water/air cooled
gpios for use by applications on the Witherspoon system.
Signed-off-by: NBrad Bishop <bradleyb@fuzziesquirrel.com>
Acked-by: NAndrew Jeffery <andrew@aj.id.au>
Signed-off-by: NJoel Stanley <joel@jms.id.au>

Add GPIO key to check presence of PCIE E2B.
Signed-off-by: NLei YU <mine260309@gmail.com>
Acked-by: NXo Wang <xow@google.com>
Signed-off-by: NJoel Stanley <joel@jms.id.au>

Signed-off-by: NLei YU <mine260309@gmail.com>
Signed-off-by: NJoel Stanley <joel@jms.id.au>

This patch adds support of external interrupt for
gpio[a..k], gpioz
Signed-off-by: NLudovic Barre <ludovic.barre@st.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

This patch adds external interrupt (exti) support
on stm32mp157c SoC.
Signed-off-by: NLudovic Barre <ludovic.barre@st.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Fix "make dtbs W=1" warns about missing reg or ranges property.
Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>

Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.

As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.

[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.htmlSigned-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>

Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.

As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.

[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.htmlSigned-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>

fix below warning about PPI interrupts configuration:
"GIC: PPI13 is secure or misconfigured"
Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>

fix below warning about PPI interrupts configuration:
"GIC: PPI13 is secure or misconfigured"
Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>

Without this property, we get this boot warning:

"L2C: device tree omits to specify unified cache"
Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>

Add interrupt-affinity property to fix below warning:
[    0.429642] CPU PMU: Failed to parse /soc/pmu/interrupt-affinity[0]
Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>

Control the Chromecast's two LEDs using PWM instead of GPIO pins. This
allows for variable brightness.
Signed-off-by: NThomas Hebb <tommyhebb@gmail.com>
Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>

On the Chromecast, the bootloader provides us with an ATAG_MEM of
start=0x01000000 and size=0x3eff8000. This is clearly incorrect, as the
range given encompasses nearly a GiB but the Chromecast only has 512MiB
of RAM! Additionally, this causes the kernel to be decompressed at
0x00008000, below the claimed beginning of RAM, and so the boot fails.

Since the existing ATAG parsing code runs before the kernel is even
decompressed and irrevocably patches the device tree, don't even try
to bypass it. Instead, use the "linux,usable-memory" property instead
of the "reg" property to define the real range. The ATAG code only
overwrites reg, but linux,usable-memory is checked first in the OF
driver, so the fact that reg gets changed makes no difference.
Signed-off-by: NThomas Hebb <tommyhebb@gmail.com>
Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>

Valve Steam Link is a consumer device built around the Marvell BG2CD SoC.
This board file enables the UART, USB and Ethernet interfaces as well as
internal I2C and SDIO, and adds SoC voltage regulator and board-specific
GPIO restart method info.

Cc: Sam Lantinga <saml@valvesoftware.com>
Signed-off-by: NAlexander Monakov <amonakov@ispras.ru>
Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>

This is useful if the board file needs to reference it.
Signed-off-by: NAlexander Monakov <amonakov@ispras.ru>
Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>

This adds most of the remaining Designware IP cores under APB trees in
the interest of documenting assignment of interrupts and memory ranges.
Signed-off-by: NAlexander Monakov <amonakov@ispras.ru>
Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>

This adds DT nodes for the Cortex-A9 MPCore SCU, local watchdog and
most importantly the global timer.
Signed-off-by: NAlexander Monakov <amonakov@ispras.ru>
Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>