Make one of them purely "English", and the other purely technical.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rather than putting quirk handling in __l2c_init(), move it out to a
separate function which individual implementations can specify.  This
helps to localise the quirks to those implementations which require
them.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rather than having this hacked into the OF initialiation function, we
can handle this via the enable function instead.  While here, clean
up that code and comments a little.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Avoid unnecessary writes to the auxiliary control register if the
register already contains the required value.  This allows us to
avoid invoking the platforms secure monitor code unnecessarily.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

We should write the auxillary control register before unlocking: the
write may be necessary to enable non-secure access to the lock
registers.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Providing an enable method gives L2 cache controllers a chance to do
special handling at enable time.  This allows us to remove a hack in
l2x0_unlock() for Marvell Aurora L2 caches.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Back in the mists of time, someone decided that it would be a good idea
to group like functions together - so all the save functions in one
place, all the resume functions in another, all the OF parsing functions
some place else.

This makes it difficult to get an overview on what a particular
implementation is doing - grouping an implementations specific functions
together makes more sense, because you can see what it's doing without
the clutter of other implementations.

Organise it according to implementation.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

There's no reason this functionality should be specific to DT, so move
it into the common initialisation function.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Pass the iomem address into this function so we don't have to keep
accessing it from a global.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rather than having a boolean and other tricks to disable some bits of
l2x0_init(), split this function into two parts: a common part shared
between OF and non-OF, and the non-OF part.

The common part can take a block of function pointers, and the cache
ID (to cope with Aurora's DT specified ID.)  Eliminate the redundant
setting of l2x0_base in the OF case, moving it to the non-OF init
function.

This allows us to localise the OF-specific initialisation handling
from the non-OF handling.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The revision namespace is specific to the L2 cache part, so don't name
these with generic identifiers, use a part specific identifier.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

cache_wait_way() is actually used to wait for a particular mask to
report clear; it's not really got much to do with cache ways at all.
Indeed, it gets used to wait for the C bit to clear on older caches.
Rename this with a more generic function name which better reflects
its purpose: l2c_wait_mask().
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Provide a generic helper function for way based operations.  These are
always background operations, and thus have to be waited for before a
new operation is commenced.  This helper extracts that requirement from
several locations in the code.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Split the cache unlock code out of l2x0_unlock().  We want to be able
to re-use this functionality later.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Provide a generic function which always calls the set_debug method.
This will be used later in the series as some work-arounds require
that the debug register be written.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rename a few things to help distinguish their function(s):
 l2x0_of_data -> l2c_init_data
 setup -> of_parse
 add of_ prefix to OF specific data
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Remove NULL initialisers, make these all __initconst structures, and
order their members in the same order as the structure declaration.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Make it easier to declare L2 cache controller DT IDs by using a macro.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

No one ever calls this function anywhere in the kernel, so let's
completely remove it from the outer cache API and turn it into an
internal-only thing.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This adds support for the Marvell Tauros3 cache controller which
is compatible with pl310 cache controller but broadcasts L1 cache
operations to L2 cache. While updating the binding documentation,
clean up the list of possible compatibles. Also reorder driver
compatibles to allow non-ARM derivated to be compatible to ARM
cache controller compatibles.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

[ this is a follow-up to this discussion:
http://archive.arm.linux.org.uk/lurker/message/20130730.230827.a1ceb12a.en.html ]
This patchset renames all uses of "bcm," name bindings to
"brcm," as they were done prior to knowing that brcm had
already been standardized as Broadcom vendor prefix
(in Documentation/devicetree/bindings/vendor-prefixes.txt).
This will not cause any churn on devices because none of
these bindings have made it into production yet.
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NChristian Daudt <csd@broadcom.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Currently we have the following output from cache-l2x0:

l2x0: 16 ways, CACHE_ID 0x410000c7, AUX_CTRL 0x32070000, Cache size: 1048576 B

Using kB for the cache size can improve readability a bit:

l2x0: 16 ways, CACHE_ID 0x410000c7, AUX_CTRL 0x32070000, Cache size: 1024 kB

While at it use pr_info.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

writel_relaxed and spin_unlock are both store operations, so we only
need to enforce store ordering in the dsb.
Signed-off-by: NWill Deacon <will.deacon@arm.com>

Rev A2 SoCs have an unorthodox memory re-mapping and this needs
to be reflected in the cache operations.
This patch adds new outer cache functions for the l2x0 driver
to support this SoC revision. It also adds a new compatible
value for the cache to enable this functionality.

Updates from V1:
- remove section 1 altogether and note that in comments
- simplify section selection caused by section 1 removal
- BUG_ON just in case section 1 shows up
Signed-off-by: NChristian Daudt <csd@broadcom.com>
Reviewed-by: NWill Deacon <will.deacon@arm.com>
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Commit b8db6b88 (ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache
ctrl) moved the masking of the part ID which caused the RTL version to be
lost. Commit 6248d060 (ARM: 7545/1: cache-l2x0: make outer_cache_fns a
field of l2x0_of_data) changed how .set_debug is initialized. Both commits
break commit 74ddcdb8 (ARM: 7608/1: l2x0: Only set .set_debug
on PL310 r3p0 and earlier) which uses the RTL version to conditionally set
.set_debug function pointer. Commit b8db6b88 also caused the printed cache
ID to be missing the version information.

Fix this by reverting how the part number is masked so the RTL version
info is maintained. The cache-id-part DT property does not set the RTL
bits so masking them should have no effect. Also, re-arrange the order
of the function pointer init so the .set_debug function can be overridden.
Reported-by: NPaolo Pisati <paolo.pisati@canonical.com>
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The use of writel instead of writel_relaxed lead to deadlock in some
situation (SMP on Armada 370 for instance). The use of writel_relaxed
as it was done in the rest of this driver fixes this bug.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch fixes a bug for Aurora L2 cache controller when the
write-through mode is enable. For the clean operation even if we don't
have to flush the lines we still need to invalidate them.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

PL310 errata work-arounds using .set_debug function are only needed on
r3p0 and earlier, so check the rev and only set .set_debug on older revs.

Avoiding debug register accesses fixes aborts on non-secure platforms
like highbank. It is assumed that non-secure platforms needing these
work-arounds have already implemented .set_debug with secure monitor
calls.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Aurora Cache Controller was designed to be compatible with the ARM L2
Cache Controller. It comes with some difference or improvement such
as:
- no cache id part number available through hardware (need to get it
  by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning
  maintenance operations on L1 are broadcasted to the L2 and L2
  performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and
  can be done on a range inside a page and are not limited to a cache
  line.
Tested-and-Reviewed-by: NLior Amsalem <alior@marvell.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NYehuda Yitschak <yehuday@marvell.com>
Reviewed-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Instead of having multiple functions belonging to outer_cache and
filling this structure on the fly, use a outer_cache_fns field inside
l2x0_of_data and just memcopy it into outer_cache depending of the
type of the l2x0 cache. For non DT case, the former code was kept.

[rmk: fixed a style issue]
Tested-and-Reviewed-by: NYehuda Yitschak <yehuday@marvell.com>
Tested-and-Reviewed-by: NLior Amsalem <alior@marvell.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

There is a bug if l2x0 controller has been enabled when calling
l2x0_init, the aux ctrl register will not be saved in l2x0_saved_regs.
Therefore we will use uninitialized l2x0_saved_regs.aux_ctrl for
resuming later.

In this patch, the aux ctrl value is read and saved after it is
initialized. So we have the real value being set for resuming.

Link: http://lkml.kernel.org/r/1336046857-24133-1-git-send-email-ylmao@marvell.comSigned-off-by: NYilu Mao <ylmao@marvell.com>
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This prepares *of_device_id.data becoming const. Without this change the
following warning would occur:

	arch/arm/mm/cache-l2x0.c: In function 'l2x0_of_init':
	arch/arm/mm/cache-l2x0.c:573:7: warning: assignment discards 'const' qualifier from pointer target type [enabled by default]

though.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>

PL310 errata #588369 and #727915 require writes to the debug registers
of the cache controller to work around known problems. Writing these
registers on L220 may cause deadlock, so ensure that we only perform
this operation when we identify a PL310 at probe time.

Cc: stable@vger.kernel.org
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The workaround for PL310 erratum #753970 can lead to deadlock on systems
with an L220 cache controller.

This patch makes the workaround effective only when the cache controller
is identified as a PL310 at probe time.

Cc: stable@vger.kernel.org
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

__u32 exists to avoid namespace clashes with userspace programs.  It
should not be used outside header files, so convert to use u32 instead.
Also, don't mix uint32_t and __u32 - use the same type throughout the
file for consistency.
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The Kconfig options for the PL310 errata workarounds do not use a
consistent naming scheme for either the config option or the bool
description.

This patch tidies up the options by ensuring that the bool descriptions
are prefixed with "PL310 errata:" and the config options are prefixed
with PL310_ERRATA_, making it much clearer in menuconfig as to what the
workarounds are for.
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

we save the l2x0 registers at the first initialization, and platform codes
can get them to restore l2x0 status after wakeup.

Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Reviewed-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

this patch fixes the error in Rob Herring's
ARM: 7009/1: l2x0: Add OF based initialization
http://www.spinics.net/lists/arm-kernel/msg131123.html
it has been in rmk/for-next with commit 41c86ff5b

Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Acked-by: NRob Herring <robherring2@gmail.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

using cpu_relax in busy loops is a well-known idiom in the kernel.
It's more for documentation purposes than technically needed here.
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Reviewed-by: NJamie Iles <jamie@jamieiles.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This adds probing for ARM L2x0 cache controllers via device tree. Support
includes the L210, L220, and PL310 controllers. The binding allows setting
up cache RAM latencies and filter addresses (PL310 only).
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NOlof Johansson <olof@lixom.net>
Acked-by: NBarry Song <21cnbao@gmail.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>