1. 23 11月, 2011 1 次提交
    • D
      Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~keithp/linux into drm-fixes · cdaeb578
      Dave Airlie 提交于
      * 'drm-intel-fixes' of git://people.freedesktop.org/~keithp/linux: (25 commits)
        drm/i915: Fix inconsistent backlight level during disabled
        drm, i915: Fix memory leak in i915_gem_busy_ioctl().
        drm/i915: Use DPCD value for max DP lanes.
        drm/i915: Initiate DP link training only on the lanes we'll be using
        drm/i915: Remove trailing white space
        drm/i915: Try harder during dp pattern 1 link training
        drm/i915: Make DP prepare/commit consistent with DP dpms
        drm/i915: Let panel power sequencing hardware do its job
        drm/i915: Treat PCH eDP like DP in most places
        drm/i915: Remove link_status field from intel_dp structure
        drm/i915: Move common PCH_PP_CONTROL setup to ironlake_get_pp_control
        drm/i915: Module parameters using '-1' as default must be signed type
        drm/i915: Turn on another required clock gating bit on gen6.
        drm/i915: Turn on a required 3D clock gating bit on Sandybridge.
        drm/i915: enable cacheable objects on Ivybridge
        drm/i915: add constants to size fence arrays and fields
        drm/i915: Ivybridge still has fences!
        drm/i915: forcewake warning fixes in debugfs
        drm/i915: Fix object refcount leak on mmappable size limit error path.
        drm/i915: Use mode_config.mutex in ironlake_panel_vdd_work
        ...
      cdaeb578
  2. 20 11月, 2011 1 次提交
    • M
      drm/radeon/kms: add a CS ioctl flag not to rewrite tiling flags in the CS · e70f224c
      Marek Olšák 提交于
      This adds a new optional chunk to the CS ioctl that specifies optional flags
      to the CS parser. Why this is useful is explained below. Note that some regs
      no longer need the NOP relocation packet if this feature is enabled.
      Tested on r300g and r600g with this flag disabled and enabled.
      
      Assume there are two contexts sharing the same mipmapped tiled texture.
      One context wants to render into the first mipmap and the other one
      wants to render into the last mipmap. As you probably know, the hardware
      has a MACRO_SWITCH feature, which turns off macro tiling for small mipmaps,
      but that only applies to samplers.
      (at least on r300-r500, though later hardware likely behaves the same)
      
      So we want to just re-set the tiling flags before rendering (writing
      packets), right? ... No. The contexts run in parallel, so they may
      set the tiling flags simultaneously and then fire their command streams
      also simultaneously. The last one setting the flags wins, the other one
      loses.
      
      Another problem is when one context wants to render into the first and
      the last mipmap in one CS. Impossible. It must flush before changing
      tiling flags and do the rendering into the smaller mipmaps in another CS.
      
      Yet another problem is that writing copy_blit in userspace would be a mess
      involving re-setting tiling flags to please the kernel, and causing races
      with other contexts at the same time.
      
      The only way out of this is to send tiling flags with each CS, ideally
      with each relocation. But we already do that through the registers.
      So let's just use what we have in the registers.
      Signed-off-by: NMarek Olšák <maraeo@gmail.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      e70f224c
  3. 18 11月, 2011 2 次提交
  4. 17 11月, 2011 9 次提交
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  6. 14 11月, 2011 2 次提交
  7. 13 11月, 2011 1 次提交
  8. 11 11月, 2011 21 次提交