New microblaze systems uses two buses. One for memories
and flashes and the second for low-speed peripherals
which can run on different CLK. This is the reason
why the kernel is trying to read clock-frequency
directly from node. If there is then the kernel will
work with it. If not then cpu CLK is used.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Microblaze little-endian toolchain exports __MICROBLAZEEL__
which is used in the kernel to identify little/big endian.

The most of the changes are in loading values from DTB which
is always big endian.

Little endian platforms are based on new AXI bus which has
impact to early uartlite initialization.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Upcomming microblaze version will support little-endian.
Signed-off-by: NMichal Simek <monstr@monstr.eu>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>

There is missing checking agains PVR but this is not important
for now. There are some missing checking too.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

We used cache_line as cache_line_lenght. For this reason
we did cache flushing 4 times longer than was necessary.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Reviewed-by: NIngo Molnar <mingo@elte.hu>
Acked-by: NStephen Neuendorffer <stephen.neuendorffer@xilinx.com>
Acked-by: NJohn Linn <john.linn@xilinx.com>
Acked-by: NJohn Williams <john.williams@petalogix.com>
Signed-off-by: NMichal Simek <monstr@monstr.eu>