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  1. 11 8月, 2021 2 次提交
    • M
      x86/PCI: Add support for the Intel 82426EX PIRQ router · 0e8c6f56
      由 Maciej W. Rozycki 提交于 
      The Intel 82426EX ISA Bridge (IB), a part of the Intel 82420EX PCIset, 
implements PCI interrupt steering with a PIRQ router in the form of two 
PIRQ Route Control registers, available in the PCI configuration space 
at locations 0x66 and 0x67 for the PIRQ0# and PIRQ1# lines respectively.

The semantics is the same as with the PIIX router, however it is not
clear if BIOSes use register indices or line numbers as the cookie to
identify PCI interrupts in their routing tables and therefore support
either scheme.

The IB is directly attached to the Intel 82425EX PCI System Controller 
(PSC) component of the chipset via a dedicated PSC/IB Link interface 
rather than the host bus or PCI.  Therefore it does not itself appear in 
the PCI configuration space even though it responds to configuration 
cycles addressing registers it implements.  Use 82425EX's identification 
then for determining the presence of the IB.

References:

[1] "82420EX PCIset Data Sheet, 82425EX PCI System Controller (PSC) and 
    82426EX ISA Bridge (IB)", Intel Corporation, Order Number: 
    290488-004, December 1995, Section 3.3.18 "PIRQ1RC/PIRQ0RC--PIRQ 
    Route Control Registers", p. 61
Signed-off-by: NMaciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2107200213490.9461@angie.orcam.me.uk
      0e8c6f56
    • M
      x86/PCI: Add support for the ALi M1487 (IBC) PIRQ router · 1ce849c7
      由 Maciej W. Rozycki 提交于 
      The ALi M1487 ISA Bus Controller (IBC), a part of the ALi FinALi 486 
chipset, implements PCI interrupt steering with a PIRQ router[1] in the 
form of four 4-bit mappings, spread across two PCI INTx Routing Table 
Mapping Registers, available in the port I/O space accessible indirectly 
via the index/data register pair at 0x22/0x23, located at indices 0x42 
and 0x43 for the INT1/INT2 and INT3/INT4 lines respectively.

Additionally there is a separate PCI INTx Sensitivity Register at index 
0x44 in the same port I/O space, whose bits 3:0 select the trigger mode 
for INT[4:1] lines respectively[2].  Manufacturer's documentation says 
that this register has to be set consistently with the relevant ELCR 
register[3].  Add a router-specific hook then and use it to handle this 
register.

Accesses to the port I/O space concerned here need to be unlocked by 
writing the value of 0xc5 to the Lock Register at index 0x03 
beforehand[4].  Do so then and then lock access after use for safety.

The IBC is implemented as a peer bridge on the host bus rather than a 
southbridge on PCI and therefore it does not itself appear in the PCI 
configuration space.  It is complemented by the M1489 Cache-Memory PCI 
Controller (CMP) host-to-PCI bridge, so use that device's identification 
for determining the presence of the IBC.

References:

[1] "M1489/M1487: 486 PCI Chip Set", Version 1.2, Acer Laboratories 
    Inc., July 1997, Section 4: "Configuration Registers", pp. 76-77

[2] same, p. 77

[3] same, Section 5: "M1489/M1487 Software Programming Guide", pp. 
    99-100

[4] same, Section 4: "Configuration Registers", p. 37
Signed-off-by: NMaciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2107191702020.9461@angie.orcam.me.uk
      1ce849c7
  3. 16 6月, 2021 1 次提交
  5. 21 5月, 2021 1 次提交
  7. 13 3月, 2021 1 次提交
  9. 10 3月, 2021 3 次提交
  11. 24 2月, 2021 1 次提交
  13. 17 2月, 2021 1 次提交
  15. 10 2月, 2021 1 次提交
  17. 05 12月, 2020 1 次提交
  19. 28 7月, 2020 1 次提交
  21. 10 7月, 2020 1 次提交
  23. 23 5月, 2020 1 次提交
  25. 09 5月, 2020 1 次提交
  27. 29 3月, 2020 1 次提交
  29. 12 3月, 2020 1 次提交
  31. 17 1月, 2020 1 次提交
  33. 21 11月, 2019 1 次提交
  35. 16 9月, 2019 1 次提交
  37. 11 9月, 2019 1 次提交
  39. 08 9月, 2019 1 次提交
  41. 04 9月, 2019 1 次提交
    • M
      x86/amd_nb: Add PCI device IDs for family 17h, model 70h · af4e1c5e
      由 Marcel Bocu 提交于 
      The AMD Ryzen gen 3 processors came with a different PCI IDs for the
function 3 & 4 which are used to access the SMN interface. The root
PCI address however remained at the same address as the model 30h.

Adding the F3/F4 PCI IDs respectively to the misc and link ids appear
to be sufficient for k10temp, so let's add them and follow up on the
patch if other functions need more tweaking.

Vicki Pfau sent an identical patch after I checked that no-one had
written this patch. I would have been happy about dropping my patch but
unlike for his patch series, I had already Cc:ed the x86 people and
they already reviewed the changes. Since Vicki has not answered to
any email after his initial series, let's assume she is on vacation
and let's avoid duplication of reviews from the maintainers and merge
my series. To acknowledge Vicki's anteriority, I added her S-o-b to
the patch.

v2, suggested by Guenter Roeck and Brian Woods:
 - rename from 71h to 70h
Signed-off-by: NVicki Pfau <vi@endrift.com>
Signed-off-by: NMarcel Bocu <marcel.p.bocu@gmail.com>
Tested-by: NMarcel Bocu <marcel.p.bocu@gmail.com>
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Acked-by: NBrian Woods <brian.woods@amd.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>	# pci_ids.h

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Cc: "Woods, Brian" <Brian.Woods@amd.com>
Cc: Clemens Ladisch <clemens@ladisch.de>
Cc: Jean Delvare <jdelvare@suse.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: linux-hwmon@vger.kernel.org
Link: https://lore.kernel.org/r/20190722174510.2179-1-marcel.p.bocu@gmail.comSigned-off-by: NGuenter Roeck <linux@roeck-us.net>
      af4e1c5e
  43. 17 8月, 2019 1 次提交
  45. 07 8月, 2019 1 次提交
  47. 12 7月, 2019 1 次提交
    • L
      PCI: Enable NVIDIA HDA controllers · b516ea58
      由 Lukas Wunner 提交于 
      Many NVIDIA GPUs can be configured as either a single-function video device
or a multi-function device with video at function 0 and an HDA audio
controller at function 1.  The HDA controller can be enabled or disabled by
a bit in the function 0 config space.

Some BIOSes leave the HDA disabled, which means the HDMI connector from the
NVIDIA GPU may not work.  Sometimes the BIOS enables the HDA if an HDMI
cable is connected at boot time, but that doesn't handle hotplug cases.

Enable the HDA controller on device enumeration and resume and re-read the
header type, which tells us whether the GPU is a multi-function device.

This quirk is limited to NVIDIA PCI devices with the VGA Controller device
class.  This is expected to correspond to product configurations where the
NVIDIA GPU has connectors attached.  Other products where the device class
is 3D Controller are expected to correspond to configurations where the
NVIDIA GPU is dedicated (dGPU) and has no connectors.  See original post
(URL below) for more details.

This commit takes inspiration from an earlier patch by Daniel Drake.

Link: https://lore.kernel.org/r/20190708051744.24039-1-drake@endlessm.com v2
Link: https://lore.kernel.org/r/20190613063514.15317-1-drake@endlessm.com v1
Link: https://devtalk.nvidia.com/default/topic/1024022
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75985Signed-off-by: NLukas Wunner <lukas@wunner.de>
Signed-off-by: NDaniel Drake <drake@endlessm.com>
[bhelgaas: commit log, log message, return early if already enabled]
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Cc: Aaron Plattner <aplattner@nvidia.com>
Cc: Peter Wu <peter@lekensteyn.nl>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: Karol Herbst <kherbst@redhat.com>
Cc: Maik Freudenberg <hhfeuer@gmx.de>
      b516ea58
  49. 09 7月, 2019 1 次提交
  51. 10 6月, 2019 1 次提交
  53. 02 2月, 2019 2 次提交
  55. 18 12月, 2018 1 次提交
  57. 12 11月, 2018 1 次提交
  59. 08 11月, 2018 2 次提交
  61. 28 9月, 2018 1 次提交
  63. 19 9月, 2018 1 次提交
  65. 18 9月, 2018 1 次提交
  67. 04 9月, 2018 1 次提交
  69. 15 8月, 2018 1 次提交