1. 01 5月, 2020 5 次提交
  2. 22 4月, 2020 1 次提交
    • V
      net: stmmac: Enable SERDES power up/down sequence · b9663b7c
      Voon Weifeng 提交于
      This patch is to enable Intel SERDES power up/down sequence. The SERDES
      converts 8/10 bits data to SGMII signal. Below is an example of
      HW configuration for SGMII mode. The SERDES is located in the PHY IF
      in the diagram below.
      
      <-----------------GBE Controller---------->|<--External PHY chip-->
      +----------+         +----+            +---+           +----------+
      |   EQoS   | <-GMII->| DW | < ------ > |PHY| <-SGMII-> | External |
      |   MAC    |         |xPCS|            |IF |           | PHY      |
      +----------+         +----+            +---+           +----------+
             ^               ^                 ^                ^
             |               |                 |                |
             +---------------------MDIO-------------------------+
      
      PHY IF configuration and status registers are accessible through
      mdio address 0x15 which is defined as mdio_adhoc_addr. During D0,
      The driver will need to power up PHY IF by changing the power state
      to P0. Likewise, for D3, the driver sets PHY IF power state to P3.
      Signed-off-by: NVoon Weifeng <weifeng.voon@intel.com>
      Signed-off-by: NOng Boon Leong <boon.leong.ong@intel.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b9663b7c
  3. 31 3月, 2020 3 次提交
  4. 18 2月, 2020 1 次提交
  5. 07 2月, 2020 1 次提交
  6. 14 1月, 2020 1 次提交
  7. 10 1月, 2020 1 次提交
  8. 14 10月, 2019 1 次提交
  9. 12 9月, 2019 1 次提交
  10. 28 8月, 2019 4 次提交
  11. 28 7月, 2019 1 次提交
    • T
      net: stmmac: Make MDIO bus reset optional · 1a981c05
      Thierry Reding 提交于
      The Tegra EQOS driver already resets the MDIO bus at probe time via the
      reset GPIO specified in the phy-reset-gpios device tree property. There
      is no need to reset the bus again later on.
      
      This avoids the need to query the device tree for the snps,reset GPIO,
      which is not part of the Tegra EQOS device tree bindings. This quiesces
      an error message from the generic bus reset code if it doesn't find the
      snps,reset related delays.
      Signed-off-by: NThierry Reding <treding@nvidia.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      1a981c05
  12. 05 6月, 2019 1 次提交
    • T
      treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 291 · 4fa9c49f
      Thomas Gleixner 提交于
      Based on 2 normalized pattern(s):
      
        this program is free software you can redistribute it and or modify
        it under the terms and conditions of the gnu general public license
        version 2 as published by the free software foundation this program
        is distributed in the hope it will be useful but without any
        warranty without even the implied warranty of merchantability or
        fitness for a particular purpose see the gnu general public license
        for more details the full gnu general public license is included in
        this distribution in the file called copying
      
        this program is free software you can redistribute it and or modify
        it under the terms and conditions of the gnu general public license
        version 2 as published by the free software foundation this program
        is distributed in the hope [that] it will be useful but without any
        warranty without even the implied warranty of merchantability or
        fitness for a particular purpose see the gnu general public license
        for more details the full gnu general public license is included in
        this distribution in the file called copying
      
      extracted by the scancode license scanner the SPDX license identifier
      
        GPL-2.0-only
      
      has been chosen to replace the boilerplate/reference in 57 file(s).
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Reviewed-by: NAlexios Zavras <alexios.zavras@intel.com>
      Reviewed-by: NAllison Randal <allison@lohutok.net>
      Cc: linux-spdx@vger.kernel.org
      Link: https://lkml.kernel.org/r/20190529141901.515993066@linutronix.deSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      4fa9c49f
  13. 01 5月, 2019 1 次提交
  14. 30 4月, 2019 1 次提交
  15. 19 4月, 2019 1 次提交
    • S
      stmmac: pci: Adjust IOT2000 matching · e0c1d14a
      Su Bao Cheng 提交于
      Since there are more IOT2040 variants with identical hardware but
      different asset tags, the asset tag matching should be adjusted to
      support them.
      
      For the board name "SIMATIC IOT2000", currently there are 2 types of
      hardware, IOT2020 and IOT2040. The IOT2020 is identified by its unique
      asset tag. Match on it first. If we then match on the board name only,
      we will catch all IOT2040 variants. In the future there will be no other
      devices with the "SIMATIC IOT2000" DMI board name but different
      hardware.
      Signed-off-by: NSu Bao Cheng <baocheng.su@siemens.com>
      Reviewed-by: NJan Kiszka <jan.kiszka@siemens.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      e0c1d14a
  16. 12 1月, 2019 1 次提交
    • J
      net: stmmac: Fix PCI module removal leak · 6dea7e18
      Jose Abreu 提交于
      Since commit b7d0f08e, the enable / disable of PCI device is not
      managed which will result in IO regions not being automatically unmapped.
      As regions continue mapped it is currently not possible to remove and
      then probe again the PCI module of stmmac.
      
      Fix this by manually unmapping regions on remove callback.
      
      Changes from v1:
      - Fix build error
      
      Cc: Joao Pinto <jpinto@synopsys.com>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Fixes: b7d0f08e ("net: stmmac: Fix WoL for PCI-based setups")
      Signed-off-by: NJose Abreu <joabreu@synopsys.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      6dea7e18
  17. 14 8月, 2018 1 次提交
    • A
      net: stmmac: mark PM functions as __maybe_unused · 81a8b079
      Arnd Bergmann 提交于
      The newly added suspend/resume functions cause a build warning
      when CONFIG_PM is disabled:
      
      drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c:324:12: error: 'stmmac_pci_resume' defined but not used [-Werror=unused-function]
      drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c:306:12: error: 'stmmac_pci_suspend' defined but not used [-Werror=unused-function]
      
      Mark them as __maybe_unused so gcc can drop them silently.
      
      Fixes: b7d0f08e ("net: stmmac: Fix WoL for PCI-based setups")
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      81a8b079
  18. 02 8月, 2018 1 次提交
    • J
      net: stmmac: Fix WoL for PCI-based setups · b7d0f08e
      Jose Abreu 提交于
      WoL won't work in PCI-based setups because we are not saving the PCI EP
      state before entering suspend state and not allowing D3 wake.
      
      Fix this by using a wrapper around stmmac_{suspend/resume} which
      correctly sets the PCI EP state.
      Signed-off-by: NJose Abreu <joabreu@synopsys.com>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Joao Pinto <jpinto@synopsys.com>
      Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b7d0f08e
  19. 23 6月, 2017 5 次提交
  20. 09 5月, 2017 4 次提交
  21. 03 5月, 2017 1 次提交
  22. 22 3月, 2017 2 次提交
  23. 14 3月, 2017 1 次提交