Originally, due to the restriction from PSP and SMU, VF has
to send message to hypervisor driver to handle powerplay
change which is complicated and redundant. Currently, SMU
and PSP can support VF to directly handle powerplay
change by itself. Therefore, the old code about the handshake
between VF and PF to handle powerplay will be removed and VF
will use new the registers below to handshake with SMU.
mmMP1_SMN_C2PMSG_101: register to handle SMU message
mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
mmMP1_SMN_C2PMSG_103: register to handle SMU response

v2: remove module parameter pp_one_vf
v3: fix the parens
v4: forbid vf to change smu feature
v5: use hwmon_attributes_visible to skip sepicified hwmon atrribute
v6: change skip condition at vega10_copy_table_to_smc
Signed-off-by: NYintian Tao <yttao@amd.com>
Acked-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Updated UMC 6.1 function set to support UMC 6.1.1 and 6.1.2 devices
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NJohn Clements <john.clements@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

the unit of variable AverageGfxActivity defined in smu12 metrics
struct is centi, so the retrieved value should be divided by 100 before
return.
Signed-off-by: NXiaomeng Hou <Xiaomeng.Hou@amd.com>
Reviewed-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

implement sensor interface of feature mask for debugfs.
Signed-off-by: NXiaomeng Hou <Xiaomeng.Hou@amd.com>
Reviewed-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

implement smu12 get_clk_freq interface to get clock frequency like
MCLK/SCLK.
Signed-off-by: NXiaomeng Hou <Xiaomeng.Hou@amd.com>
Reviewed-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

add sensor interface of get gpu temperature for debugfs.
Signed-off-by: NXiaomeng Hou <Xiaomeng.Hou@amd.com>
Reviewed-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This is needed for coming asic init on performing gpu reset.

V2: use non-asic specific programing way
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

It may cause timeout waiting for sem acquire in VM flush when using
invalidate semaphore for picasso. So it needs to avoid using invalidate
semaphore for piasso.
Signed-off-by: Nchangzhu <Changfeng.Zhu@amd.com>
Reviewed-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Switch to baco reset method for ras recovery if the PMFW supported.
If not, keep the original reset method.

v2: revise the condition
Signed-off-by: NLe Ma <le.ma@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Abort the message issuing if the SMU was not in the right state.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

As the check may be done with purpose and the warning
output will be confusing.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

To avoid a compiler warning.
Reviewed-by: NZhan Liu <zhan.liu@amd.com>
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

this fix the regression caused by asd/ta loading sequence
adjustment recently. asd/ta loading was move out from
hw_start and should also be applied to psp_resume.
otherwise those fw loading will be ignored in resume phase.

v2: add the mutex unlock for asd loading failure case
v3: merge the error handling to failed tag
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NGuchun Chen <guchun.chen@amd.com>
Reviewed-by: NLe Ma <Le.Ma@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This reverts commit a4840d91.

Reverting due to power efficiency issues seen on Raven 1 and 2
when DPG mode is enabled.
Signed-off-by: NThong Thai <thong.thai@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This allows to invalidate VM entries without taking the reservation lock.

v3: use -EBUSY
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Don't add the VM update fences to the resv object and remove
the handling to stop implicitely syncing to them.

Ongoing updates prevent page tables from being evicted and we manually
block for all updates to complete before releasing PDs and PTS.

This way we can do updates even without the resv obj locked.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Allows us to reduce the overhead while syncing to fences a bit.

v2: also drop adev parameter from the functions
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

When a page tables needs to be evicted the VM code should
decide if that is possible or not.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

BACO feature must be kept enabled to allow entry into
BACO state in SMU during runtime suspend.
Signed-off-by: NAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Tested-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
To quickly validate whether DMCUB is running and accepting commands for
offload testing we want to intercept a common sequence as part of
modeset programming.

[How]
OTG enable will cause the most impact in terms of golden register
changes and it's a single register write.

This approach was previously done in dcn10 code when it was shared with
dcn20 but it wasn't ported over to the dcn20 code.

Port over start, execute and wait sequence into dcn20_optc.
Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
When setting lttpr mode, the new mode to bet is not logged properly.

[How]
Update log message to show the right mode.
Signed-off-by: Nabdoulaye berthe <abdoulaye.berthe@amd.com>
Reviewed-by: NGeorge Shen <George.Shen@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

In preparation for further changes
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NChris Park <Chris.Park@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
It seems always request passive flip on RN due to incorrect compare
clock state to determine optization.

[How]
Instead of calling memcmp, compare clock state member to determine the
condition.
Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
When a timeout occurs after a DEFER, some devices require more retries
than in the case of a regular timeout.

[How]
In a timeout occurrence, check whether a DEFER has occurred before the
timeout and retry MAX_DEFER_RETRIES retries times instead of
MAX_TIMEOUT_RETRIES.
Signed-off-by: NGeorge Shen <george.shen@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NAbdoulaye Berthe <Abdoulaye.Berthe@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Currently we require HDR_MULT >= 1.0
There are scenarios where we need < 1.0

[How]
Only guard against 0 - it will black-screen image.
It is up to higher-level logic to decide what HDR_MULT
values are allowed in each particular case.
Signed-off-by: NKrunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Need support for more color management in 10bit
surface.

[How]
Provide support for DePQ for 10bit surface
Signed-off-by: NReza Amini <Reza.Amini@amd.com>
Reviewed-by: NKrunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Value obtained from DV is not allowing 8k60 CTA mode with DSC to
pass, after checking real value being used in hw, find out that
correct value is 3600, which will allow that mode.
Signed-off-by: NEric Yang <Eric.Yang2@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Screen tearing is present in tests when setting the frame rate to
certain fps

[How]
Revert previous optimizations for low frame rates.
Signed-off-by: NAmanda Liu <amanda.liu@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Cursor position needs to take into account plane scaling as well.

[How]
Translate cursor coords from stream space to plane space.
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Acked-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
It is causing green Line at the bottom of SDR 480p
MPO playback

[How]
Limit workaround to vertical > 512
Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

dc needs to expose its internal dsc policy.
Signed-off-by: NWenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: NNikola Cornij <Nikola.Cornij@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
add_dsc_to_stream_resource could be called for validation.
Failing validation is completely fine.
However failing it inside commit streams is bad.
This code could be triggered for both contexts.
The function itself cannot distinguish the caller, which
makes it impossible to output the log only in the
meaningful case (commit streams).
Signed-off-by: NWenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: NNikola Cornij <Nikola.Cornij@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
Need to support 6 bpp for 420 pixel encoding only.

[how]
Add a dc function to determine what bpp range can be supported
for given pixel encoding.
Signed-off-by: NWenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: NNikola Cornij <Nikola.Cornij@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
I was advised that we don't need this call of program_front_end, as
earlier and later calls in the same sequence are sufficient.

[How]
Remove first call of program_front_end in dc_commit_state_no_check.
Signed-off-by: NNoah Abradjian <noah.abradjian@amd.com>
Reviewed-by: NYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
I was advised that we may need to check for mpcc idle in more cases
than just when opp_changed is true. Also, mpcc_inst is equal to
pipe_idx, so remove for loop.

[How]
Remove opp_changed flag check and mpcc_inst loop.
Signed-off-by: NNoah Abradjian <noah.abradjian@amd.com>
Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
When training with repeater the aux read interval must be set to
repeater specific aux_red_interval. This value is always 100us for CR.

[How]
Check for repeater when setting the aux_rd_interval in channel
equalization.
Use the right offset in the aux_rd_interval array
Signed-off-by: Nabdoulaye berthe <abdoulaye.berthe@amd.com>
Reviewed-by: NWenjing Liu <Wenjing.Liu@amd.com>
Acked-by: NGeorge Shen <George.Shen@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
MPCC programming was being missed during certain split pipe enables due
to full_update flag not being true. This caused a momentary flash on
half the screen. After discussion, determined we should not have that
flag check within update_mpcc, as it should always perform full
programming when called.

[How]
Remove flag check. We call update_blending within insert_plane, so we
do not need to replace its call from the if block.
Signed-off-by: NNoah Abradjian <noah.abradjian@amd.com>
Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
DF team has produced more optimized sr latency numbers, for lpddr4

[How]
change the sr laency in the lpddr4 wm table to the new latency
number
Signed-off-by: NJoseph Gravenor <joseph.gravenor@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Scratch registers are limited on the DMCUB and we have an expanding
list of state to track between driver and DMCUB.

[How]
Place shared state in cache window 6. The cache window size is aligned
to the size of the cache line on the DMCUB to make it easy to
invalidate.

The shared state is intended to be read only from driver side so
it's been marked as const.

The use of volatile is intentional. The memory for the shared firmware
state is memory mapped from the framebuffer memory. The DMCUB will
flush its cache after modifying the region. There's no way for x86
to known whether this data is stale or not so we want to intentionally
disable optimization to force the read at every access.
Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>