1. 21 9月, 2018 6 次提交
  2. 18 9月, 2018 1 次提交
    • J
      IB/rxe: Revise the ib_wr_opcode enum · 9a59739b
      Jason Gunthorpe 提交于
      This enum has become part of the uABI, as both RXE and the
      ib_uverbs_post_send() command expect userspace to supply values from this
      enum. So it should be properly placed in include/uapi/rdma.
      
      In userspace this enum is called 'enum ibv_wr_opcode' as part of
      libibverbs.h. That enum defines different values for IB_WR_LOCAL_INV,
      IB_WR_SEND_WITH_INV, and IB_WR_LSO. These were introduced (incorrectly, it
      turns out) into libiberbs in 2015.
      
      The kernel has changed its mind on the numbering for several of the IB_WC
      values over the years, but has remained stable on IB_WR_LOCAL_INV and
      below.
      
      Based on this we can conclude that there is no real user space user of the
      values beyond IB_WR_ATOMIC_FETCH_AND_ADD, as they have never worked via
      rdma-core. This is confirmed by inspection, only rxe uses the kernel enum
      and implements the latter operations. rxe has clearly never worked with
      these attributes from userspace. Other drivers that support these opcodes
      implement the functionality without calling out to the kernel.
      
      To make IB_WR_SEND_WITH_INV and related work for RXE in userspace we
      choose to renumber the IB_WR enum in the kernel to match the uABI that
      userspace has bee using since before Soft RoCE was merged. This is an
      overall simpler configuration for the whole software stack, and obviously
      can't break anything existing.
      Reported-by: NSeth Howell <seth.howell@intel.com>
      Tested-by: NSeth Howell <seth.howell@intel.com>
      Fixes: 8700e3e7 ("Soft RoCE driver")
      Cc: <stable@vger.kernel.org>
      Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      9a59739b
  3. 14 9月, 2018 1 次提交
  4. 13 9月, 2018 2 次提交
  5. 11 9月, 2018 7 次提交
  6. 07 9月, 2018 1 次提交
  7. 06 9月, 2018 8 次提交
  8. 05 9月, 2018 7 次提交
  9. 04 9月, 2018 1 次提交
  10. 31 8月, 2018 3 次提交
  11. 30 8月, 2018 1 次提交
    • M
      arm/arm64: smccc-1.1: Handle function result as parameters · 755a8bf5
      Marc Zyngier 提交于
      If someone has the silly idea to write something along those lines:
      
      	extern u64 foo(void);
      
      	void bar(struct arm_smccc_res *res)
      	{
      		arm_smccc_1_1_smc(0xbad, foo(), res);
      	}
      
      they are in for a surprise, as this gets compiled as:
      
      	0000000000000588 <bar>:
      	 588:   a9be7bfd        stp     x29, x30, [sp, #-32]!
      	 58c:   910003fd        mov     x29, sp
      	 590:   f9000bf3        str     x19, [sp, #16]
      	 594:   aa0003f3        mov     x19, x0
      	 598:   aa1e03e0        mov     x0, x30
      	 59c:   94000000        bl      0 <_mcount>
      	 5a0:   94000000        bl      0 <foo>
      	 5a4:   aa0003e1        mov     x1, x0
      	 5a8:   d4000003        smc     #0x0
      	 5ac:   b4000073        cbz     x19, 5b8 <bar+0x30>
      	 5b0:   a9000660        stp     x0, x1, [x19]
      	 5b4:   a9010e62        stp     x2, x3, [x19, #16]
      	 5b8:   f9400bf3        ldr     x19, [sp, #16]
      	 5bc:   a8c27bfd        ldp     x29, x30, [sp], #32
      	 5c0:   d65f03c0        ret
      	 5c4:   d503201f        nop
      
      The call to foo "overwrites" the x0 register for the return value,
      and we end up calling the wrong secure service.
      
      A solution is to evaluate all the parameters before assigning
      anything to specific registers, leading to the expected result:
      
      	0000000000000588 <bar>:
      	 588:   a9be7bfd        stp     x29, x30, [sp, #-32]!
      	 58c:   910003fd        mov     x29, sp
      	 590:   f9000bf3        str     x19, [sp, #16]
      	 594:   aa0003f3        mov     x19, x0
      	 598:   aa1e03e0        mov     x0, x30
      	 59c:   94000000        bl      0 <_mcount>
      	 5a0:   94000000        bl      0 <foo>
      	 5a4:   aa0003e1        mov     x1, x0
      	 5a8:   d28175a0        mov     x0, #0xbad
      	 5ac:   d4000003        smc     #0x0
      	 5b0:   b4000073        cbz     x19, 5bc <bar+0x34>
      	 5b4:   a9000660        stp     x0, x1, [x19]
      	 5b8:   a9010e62        stp     x2, x3, [x19, #16]
      	 5bc:   f9400bf3        ldr     x19, [sp, #16]
      	 5c0:   a8c27bfd        ldp     x29, x30, [sp], #32
      	 5c4:   d65f03c0        ret
      Reported-by: NJulien Grall <julien.grall@arm.com>
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      755a8bf5
  12. 29 8月, 2018 2 次提交