The spi-mem layer provides a spi_mem_supports_op() function to check
whether a specific operation is supported by the controller or not.
This is much more accurate than the hwcaps selection logic based on
SPI_{RX,TX}_ flags.

Rework the hwcaps selection logic to use spi_mem_supports_op() when
nor->spimem != NULL.
Signed-off-by: NBoris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>

The m25p80 driver is actually a generic wrapper around the spi-mem
layer. Not only the driver name is misleading, but we'd expect such a
common logic to be directly available in the core. Another reason for
moving this code is that SPI NOR controller drivers should
progressively be replaced by SPI controller drivers implementing the
spi_mem_ops interface, and when the conversion is done, we should have
a single spi-nor driver directly interfacing with the spi-mem layer.

While moving the code we also fix a longstanding issue when
non-DMA-able buffers are passed by the MTD layer.
Signed-off-by: NBoris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>

spi-mem layer expects all buffers passed to it to be DMA'able. But
spi-nor layer mostly allocates buffers on stack for reading/writing to
registers and therefore are not DMA'able. Introduce bounce buffer to be
used to read/write to registers. This ensures that buffer passed to
spi-mem layer during register read/writes is DMA'able. With this change
nor->cmd-buf is no longer used, so drop it.
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: NBoris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>

While I was tempted to move it to admin-guide, as some docs
there are more userspace-faced, there are some very technical
discussions about memory error correction code from the Kernel
implementer's PoV. So, let's place it inside the driver-api
book.
Signed-off-by: NMauro Carvalho Chehab <mchehab+samsung@kernel.org>

Rename the mtd documentation files to ReST, add an
index for them and adjust in order to produce a nice html
output via the Sphinx build system.

It should be noticed that Sphinx doesn't handle very well
URLs with dots in the middle. Thankfully, internally, the '.'
char is translated to %2E, so we can jus use %2E instead of
dots, and this will work fine on both text and processed files.

At its new index.rst, let's add a :orphan: while this is not linked to
the main index.rst file, in order to avoid build warnings.
Signed-off-by: NMauro Carvalho Chehab <mchehab+samsung@kernel.org>

Add an implementation of the _is_locked operation for concatenated mtd
devices. This doesn't handle getting the lock status of a range that
spans chips, which is consistent with cfi_ppb_is_locked and
cfi_intelext_is_locked which only look at the first block in the range.
Signed-off-by: NChris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: NRichard Weinberger <richard@nod.at>

concat_lock() and concat_unlock() only differed in terms of the mtd_xx
operation they called. Refactor them to use a common helper function and
pass a boolean flag to indicate whether lock or unlock is needed.
Signed-off-by: NChris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: NRichard Weinberger <richard@nod.at>

NULL check before kfree is unneeded, so remove it.
Signed-off-by: NDing Xiang <dingxiang@cmss.chinamobile.com>
Signed-off-by: NRichard Weinberger <richard@nod.at>

Allwinner NAND controllers can make use of DMA to enhance the I/O
throughput thanks to ECC pipelining. DMA handling with A23/A33 NAND IP
is a bit different than with the older SoCs, hence the introduction of
a new compatible to handle:
* the differences between register offsets,
* the burst length change from 4 to minimum 8,
* manage SRAM accesses through MBUS with extra configuration.

Fixes: c49836f0 ("mtd: rawnand: sunxi: Add A23/A33 DMA support")
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

This reverts commit c49836f0.

The commit is wrong and its approach actually does not work. Let's
revert it in order to add the feature with a clean patch.

Fixes: c49836f0 ("mtd: rawnand: sunxi: Add A23/A33 DMA support")
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

If MTD_NAND_JZ4780 is y and MTD_NAND_JZ4780_BCH is m,
which select CONFIG_MTD_NAND_INGENIC_ECC to m, building fails:

drivers/mtd/nand/raw/ingenic/ingenic_nand.o: In function `ingenic_nand_remove':
ingenic_nand.c:(.text+0x177): undefined reference to `ingenic_ecc_release'
drivers/mtd/nand/raw/ingenic/ingenic_nand.o: In function `ingenic_nand_ecc_correct':
ingenic_nand.c:(.text+0x2ee): undefined reference to `ingenic_ecc_correct'

To fix that, the ingenic_nand and ingenic_ecc modules have been fused
into one single module.
- The ingenic_ecc.c code is now compiled in only if
  $(CONFIG_MTD_NAND_INGENIC_ECC) is set. This is now a boolean instead
  of tristate.
- To avoid changing the module name, the ingenic_nand.c file is moved to
  ingenic_nand_drv.c. Then the module name is still ingenic_nand.
- Since ingenic_ecc.c is no more a module, the module-specific macros
  have been dropped, and the functions are no more exported for use by
  the ingenic_nand driver.

Fixes: 15de8c6e ("mtd: rawnand: ingenic: Separate top-level and SoC specific code")
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Reported-by: NArnd Bergmann <arnd@arndb.de>
Reported-by: NHulk Robot <hulkci@huawei.com>
Cc: YueHaibing <yuehaibing@huawei.com>
Cc: stable@vger.kernel.org
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The 1Gb Macronix chip can have a maximum of 20 bad blocks, while
the 2Gb version has twice as many blocks and therefore the maximum
number of bad blocks is 40.

The 4Gb GigaDevice GD5F4GQ4xA has twice as many blocks as its 2Gb
counterpart and therefore a maximum of 80 bad blocks.

Fixes: 377e517b ("mtd: nand: Add max_bad_eraseblocks_per_lun info to memorg")
Reported-by: NEmil Lenngren <emil.lenngren@gmail.com>
Signed-off-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

When the system is overloaded, DMA data transfer completion occurs after
100ms. Increase the timeouts to let it the time to complete.
Signed-off-by: NAmelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: NChristophe Kerello <christophe.kerello@st.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Replace kmalloc() by a memset() followed with a kzalloc().

There is a recommendation to use zeroing allocator
rather than allocator followed by memset(0) in
./scripts/coccinelle/api/alloc/zalloc-simple.cocci
Signed-off-by: NFuqian Huang <huangfq.daxian@gmail.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Add driver for HyperBus memory controller on TI's AM654 SoC. Programming
IP is pretty simple and provides direct memory mapped access to
connected Flash devices.

Add basic support for the IP without DMA. Second chip-select is not
supported for now.
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

In case of the last page containing bitflips (ret > 0),
spinand_mtd_read() will return that number of bitflips for the last
page while it should instead return max_bitflips like it does when the
last page read returns with 0.
Signed-off-by: NWeixiong Liao <liaoweixiong@allwinnertech.com>
Reviewed-by: NBoris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
Cc: stable@vger.kernel.org
Fixes: 7529df46 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Add initial support for Paragon Technology
PN26G01Axxxxx and PN26G02Axxxxx SPI NAND

Datasheets available at
http://www.xtxtech.com/upfile/2016082517274590.pdf
http://www.xtxtech.com/upfile/2016082517282329.pdfSigned-off-by: NJeff Kletsky <git-commits@allycomm.com>
Reviewed-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

It is wanted to use MTK NAND driver with GPL-2.0 or MIT license.
But now it is only licensed as GPL-2.0, so re-license it as dual
MIT/GPL.
Signed-off-by: NXiaolei Li <xiaolei.li@mediatek.com>
Acked-by: NJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Acked-by: NRyder Lee <ryder.lee@mediatek.com>
Acked-by: NRafał Miłecki <rafal@milecki.pl>
Acked-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Acked-by: NBoris Brezillon <boris.brezillon@collabora.com>
Acked-by: NWen Yang <yellowriver2010@hotmail.com>
Acked-by: NDan Carpenter <dan.carpenter@oracle.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NRogerCC Lin <rogercc.lin@mediatek.com>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The variable block_size is being assigned to itself and to
geo->ecc_chunk_size.  Clean up the double assignment by removing
the assignment to itself.

Addresses-Coverity: ("Evaluation order violation")
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

This change adds support for brcm NAND v7.3 controller. This controller
uses a newer version of flash_dma engine and change mostly implements
these differences.
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Refactored NAND ECC and CMD address configuration code to use helper
functions.
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

If mtd_oops is in progress, switch to polling during NAND command
completion instead of relying on DMA/interrupts so that the mtd_oops
buffer can be completely written in the assigned NAND partition.
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Added a flag to indicate a panic_write so that low level drivers can
use it to take required action where applicable, to ensure oops data
gets written to assigned mtd device.
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Add support for Macronix NAND read retry.

Macronix NANDs support specific read operation for data recovery,
which can be enabled with a SET_FEATURE.
Driver checks byte 167 of Vendor Blocks in ONFI parameter page table
to see if this high-reliability function is supported.
Signed-off-by: NMason Yang <masonccyang@mxic.com.tw>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

NOTICE THAT:

"...we don't know whether we need fallthroughs or breaks here and this
is just a change to avoid having new warnings when switching to
-Wimplicit-fallthrough but this change might be entirely wrong."[1]

See the original thread of discussion here:

https://lore.kernel.org/patchwork/patch/1036251/

So, in preparation to enabling -Wimplicit-fallthrough, this patch silences
the following warnings:

drivers/mtd/nand/onenand/onenand_base.c: In function ‘onenand_check_features’:
drivers/mtd/nand/onenand/onenand_base.c:3264:6: warning: this statement may fall through [-Wimplicit-fallthrough=]
   if (ONENAND_IS_DDP(this))
      ^
drivers/mtd/nand/onenand/onenand_base.c:3284:2: note: here
  case ONENAND_DEVICE_DENSITY_2Gb:
  ^~~~
drivers/mtd/nand/onenand/onenand_base.c:3288:17: warning: this statement may fall through [-Wimplicit-fallthrough=]
   this->options |= ONENAND_HAS_UNLOCK_ALL;
drivers/mtd/nand/onenand/onenand_base.c:3290:2: note: here
  case ONENAND_DEVICE_DENSITY_1Gb:
  ^~~~

Warning level 3 was used: -Wimplicit-fallthrough=3

Also, notice that this patch doesn't change any functionality. See the
most recent thread of discussion here:

https://lore.kernel.org/patchwork/patch/1077395/

This patch is part of the ongoing efforts to enable
-Wimplicit-fallthrough.

[1] https://lore.kernel.org/lkml/20190509085318.34a9d4be@xps13/

Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Suggested-by: NBoris Brezillon <boris.brezillon@collabora.com>
Suggested-by: NKees Cook <keescook@chromium.org>
Signed-off-by: NGustavo A. R. Silva <gustavo@embeddedor.com>
Reviewed-by: NKees Cook <keescook@chromium.org>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The GigaDevice GD5F1GQ4UFxxG SPI NAND is in current production devices
and, while it has the same logical layout as the E-series devices,
it differs in the SPI interfacing in significant ways.

This support is contingent on previous commits to:

  * Add support for two-byte device IDs
  * Define macros for page-read ops with three-byte addresses

http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/Signed-off-by: NJeff Kletsky <git-commits@allycomm.com>
Reviewed-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The GigaDevice GD5F1GQ4UFxxG SPI NAND utilizes two-byte device IDs.

http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/Signed-off-by: NJeff Kletsky <git-commits@allycomm.com>
Reviewed-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

This change supports nand-ecc-step-size and nand-ecc-strength fields in
brcmnand DT node to be optional.
see: Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt

If both nand-ecc-strength and nand-ecc-step-size are not specified in
device tree node for NAND, raw NAND layer does detect ECC information by
reading ONFI extended parameter page for parts using ONFI >= 2.1.
In case of non-ONFI NAND parts there could be a nand_id table entry with
ECC information. If there is valid device tree entry for nand-ecc-strength
and nand-ecc-step-size fields it still shall override the detected values.
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The gpmi driver performance suffers from NAND operations being split
in multiple small DMA transfers. This has been forced by the NAND layer
in the former days, but now with exec_op we can use the controller as
intended.

With this patch gpmi_nfc_exec_op becomes the main entry point to NAND
operations. Here all instructions are collected and chained as separate
DMA transfers. In the end whole chain is fired and waited to be
finished. gpmi_nfc_exec_op only does the hardware operations, bad block
marker swapping and buffer scrambling is done by the callers. It's worth
noting that the nand_*_op functions always take the buffer lengths for
the data that the NAND chip actually transfers. When doing BCH we have
to calculate the net data size from the raw data size in some places.

This patch has been tested with 2048/64 and 2048/128 byte NAND on
i.MX6q. mtd_oobtest, mtd_subpagetest and mtd_speedtest run without
errors. nandbiterrs, nandpagetest and nandsubpagetest userspace tests
from mtdutils run without errors and UBIFS can successfully be mounted.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The mxs dma driver uses the flags parameter in dmaengine_prep_slave_sg() for
custom flags, but still uses the dmaengine specific names of the flags.
Do a little bit better and at least give the flag a custom name.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The mxs dma driver can do PIO transfers. A pointer to the PIO words
to transfer is passed in the struct scatterlist * argument of
dmaengine_prep_slave_sg(). It's quite ugly and non obvious to cast
u32 * to struct scatterlist * each time when calling
dmaengine_prep_slave_sg(), so add a static inline wrapper function
to be called by the user along with a description what is going on.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The DMA_PREP_INTERRUPT flag is no longer needed by the mxs DMA driver,
drop it.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The gpmi driver aggressively en/disables the clocks between operations
which has significant performance cost. Use runtime PM to get rid of
this bottleneck.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The i.MX23 specific option read code is called right after nand_scan. We
can rely on the NAND core having disabled the chipselect, so there's no
point in restoring the original chip select after NAND operations. Drop
it.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

gpmi_ecc_read_page_data uses the page parameter only for a debug printf,
so we can drop the parameter and the debug printf. Moving the oob
delivery from gpmi_ecc_read_page_data to gpmi_ecc_read_page makes the
oob_required parameter unnecessary aswell.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The driver calls nand_read_page_op without a buffer passed and then
calls chip->legacy.read_buf to read the buffer afterwards which is
the same as passing the buffer nand_read_page_op in the first place.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

this->page_buffer_virt and this->payload_virt are always set to the same
value, so drop the former and just use the latter. Same for
this->page_buffer_virt and this->payload_virt.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The "private" member of struct gpmi_nand_data isn't used anywhere.
Remove it.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

This moves the whole driver into a single C file. The filename gpmi-lib
implies that it implements library functions, but in fact there are
several cases where functions in gpmi-lib.c call back into functions in
gpmi-nand.c. With this one has to constantly jump between those two
files, so moving it into a single file improves readability, even when
the file gets quite large.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Replace the different operation tracing functions with a call to
nand_op_trace.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>