The DHCOM SoM uSD slot has an optional voltage level translator, add
DT bindings which permit the MMCI driver to detect the translator
automatically.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Ludovic Barre <ludovic.barre@st.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: linux-stm32@st-md-mailman.stormreply.com
Signed-off-by: NAlexandre Torgue <alexandre.torgue@foss.st.com>

Add "init" mux option for SDMMC1, where the CMD, CK, CKIN lines are not
configured, so they can be claimed as GPIOs early on in driver probe().
This is used for probing optional voltage level translator.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Ludovic Barre <ludovic.barre@st.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: linux-stm32@st-md-mailman.stormreply.com
Signed-off-by: NAlexandre Torgue <alexandre.torgue@foss.st.com>

The PicoITX has only one ethernet routed out, so the KS8851 is not used
at all. Disable the KS8851 and the entire FMC controller.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: NAlexandre Torgue <alexandre.torgue@foss.st.com>

The node names for devices using the pwm-leds driver follow a certain
naming scheme (now).  Parent node name is not enforced, but recommended
by DT project.

  DTC     arch/arm/boot/dts/stm32mp157c-lxa-mc1.dt.yaml
  CHECK   arch/arm/boot/dts/stm32mp157c-lxa-mc1.dt.yaml
/home/alex/build/linux/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dt.yaml: led-rgb: 'led-blue', 'led-green', 'led-red' do not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+'
        From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml
Signed-off-by: NAlexander Dahl <post@lespocky.de>
Acked-by: NAhmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@foss.st.com>

The STM32MP1 DHCOM SoM can be built with either bus voltage level shifter
or without one on the SDMMC1 interface. Because the SDMMC1 interface is
limited to 50 MHz and hence SD high-speed anyway, disable the SD feedback
clock to permit operation of the same U-Boot image on both SoM with and
without voltage level shifter.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: NAlexandre Torgue <alexandre.torgue@foss.st.com>

The default state of SD bus and clock line is logical HI. SD card IO is
open-drain and pulls the bus lines LO. Always enable the SD bus pull ups
to guarantee this behavior on DHCOM SoM. Note that on SoMs with SD bus
voltage level shifter, the pull ups are built into the level shifter,
however that has no negative impact.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: NAlexandre Torgue <alexandre.torgue@foss.st.com>

The GPIO hog flags are ignored by gpiolib-of.c now, set the flags to 0.
Since GPIO_ACTIVE_HIGH is defined as 0, this change only increases the
correctness of the DT.

Fixes: fde180f0 ("ARM: dts: stm32: Add DHSOM based DRC02 board")
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: NAlexandre Torgue <alexandre.torgue@foss.st.com>

The GPIO hog flags are ignored by gpiolib-of.c now, set the flags to 0.
Due to a change in gpiolib-of.c, setting flags to GPIO_ACTIVE_LOW and
using output-low DT property leads to the GPIO being set high instead.

Fixes: ac68793f ("ARM: dts: stm32: Add DHCOM based PicoITX board")
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: NAlexandre Torgue <alexandre.torgue@foss.st.com>

The GPIO hog node name should match regex '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$',
make it so and fix the following two make dtbs_check warnings:

arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dt.yaml: hog-usb-port-power: $nodename:0: 'hog-usb-port-power' does not match '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$'
arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dt.yaml: hog-usb-hub: $nodename:0: 'hog-usb-hub' does not match '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$'

Fixes: ac68793f ("ARM: dts: stm32: Add DHCOM based PicoITX board")
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: NAlexandre Torgue <alexandre.torgue@foss.st.com>

The DRC02 has no use for the on-SoM touchscreen controller, and the
on-SoM touchscreen controller may not even be populated, which then
results in error messages in kernel log. Disable the touchscreen
controller in DT.

Fixes: fde180f0 ("ARM: dts: stm32: Add DHSOM based DRC02 board")
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: NAlexandre Torgue <alexandre.torgue@foss.st.com>

The uSD slot has no WP detection, disable it.

Fixes: 34e0c784 ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board")
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: NAlexandre Torgue <alexandre.torgue@foss.st.com>

The DHCOM SoM uSD slot card detect signal is connected to GPIO PG1,
describe it in the DT.

Fixes: 34e0c784 ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board")
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: NAlexandre Torgue <alexandre.torgue@foss.st.com>

The uSD card detect signal on the DH DRC02 is active-high, with
a default pull down resistor on the board. Invert the polarity.

Fixes: fde180f0 ("ARM: dts: stm32: Add DHSOM based DRC02 board")
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
--
Note that this could not be tested on prototype SoMs, now that it is
tested, this issue surfaced, so it needs to be fixed.
Signed-off-by: NAlexandre Torgue <alexandre.torgue@foss.st.com>

The DTB magic marker is stored as a 32-bit big-endian value, and thus
depends on the CPU's endianness.  Add a macro to define this value in
native endianness, to reduce #ifdef clutter and (future) duplication.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NArd Biesheuvel <ardb@kernel.org>
Reviewed-by: NNicolas Pitre <nico@fluxnic.net>
Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>

The dbgadtb macro is passed the size of the appended DTB, not the end
address.

Fixes: c03e4147 ("ARM: 9010/1: uncompress: Print the location of appended DTB")
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>

DTB stores all values as 32-bit big-endian integers.
Add a macro to convert such values to native CPU endianness, to reduce
duplication.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NArd Biesheuvel <ardb@kernel.org>
Reviewed-by: NNicolas Pitre <nico@fluxnic.net>
Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>

'pnx,timeout' is unused, undocumented and 'pnx' is not a vendor prefix,
so let's remove it.
Acked-by: NVladimir Zapolskiy <vz@mleia.com>
Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
Link: https://lore.kernel.org/r/20201210175238.2721550-1-robh@kernel.orgSigned-off-by: NRob Herring <robh@kernel.org>

The check_spi_bus_bridge() in scripts/dtc/checks.c requires that the node
have "spi-slave" property must with "#address-cells = <0>" and
"#size-cells = <0>". But currently both "#address-cells" and "#size-cells"
properties are deleted, the corresponding default values are 2 and 1. As a
result, the check fails and below warnings is displayed.

arch/arm/boot/dts/mmp2.dtsi:472.23-480.6: Warning (spi_bus_bridge): \
/soc/apb@d4000000/spi@d4037000: incorrect #address-cells for SPI bus
  also defined at arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts:225.7-237.3
arch/arm/boot/dts/mmp2.dtsi:472.23-480.6: Warning (spi_bus_bridge): \
/soc/apb@d4000000/spi@d4037000: incorrect #size-cells for SPI bus
  also defined at arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts:225.7-237.3
arch/arm/boot/dts/mmp2-olpc-xo-1-75.dtb: Warning (spi_bus_reg): \
Failed prerequisite 'spi_bus_bridge'

Because the value of "#size-cells" is already defined as zero in the node
"ssp3: spi@d4037000" in arch/arm/boot/dts/mmp2.dtsi. So we only need to
explicitly add "#address-cells = <0>" and keep "#size-cells" no change.
Signed-off-by: NZhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20201207084752.1665-2-thunder.leizhen@huawei.com'
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add the specific compat string for the smpctrl registers to the
SSD201/SSD202D common dtsi.
Signed-off-by: NDaniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20201201134330.3037007-10-daniel@0x0f.com'
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add the smpctrl registers to the infinity2m dtsi so that the
second CPU can be enabled on chips in this family.
Signed-off-by: NDaniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20201201134330.3037007-9-daniel@0x0f.com'
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add a dts for the Honestar ssd201htv2 devkit.
This is for the board populated with a SSD202D.
Signed-off-by: NDaniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20201201134330.3037007-8-daniel@0x0f.com'
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add a chip level dtsi for the SigmaStar SSD202D
Signed-off-by: NDaniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20201201134330.3037007-7-daniel@0x0f.com'
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The SSD201 and SSD202D are basically the same chip with a different DDR die
packaged (64MB DDR2 or 128MB DDR3).

This patch adds a shared dtsi for the common parts of these chips like
gpio, pinctrl etc.
Signed-off-by: NDaniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20201201134330.3037007-6-daniel@0x0f.com'
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The infinity2m series of chips are like the other Mstar/Sigmastar
chips in that they have a Cortex A7 system with DDR memory integrated
in a single package.

The infinity2m chips are intended for recording the incoming streams
from IP cameras. So instead of video encoders they have video decoders,
instead of a camera interface they have display hardware and so on.

Aside from the above points the big difference about these chips is that
they include a second Cortex A7 core.
Signed-off-by: NDaniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20201201134330.3037007-5-daniel@0x0f.com'
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Fill in the properties needed to use the GPIO controller
in the infinity and infinity3 chips.
Signed-off-by: NDaniel Palmer <daniel@0x0f.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20201129110803.2461700-6-daniel@0x0f.com'
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The GPIO controller is at the same address in all of the
currently known chips so create a node for it in the base
dtsi.

Some extra properties are needed to actually use it so
disable it by default.
Signed-off-by: NDaniel Palmer <daniel@0x0f.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20201129110803.2461700-5-daniel@0x0f.com'
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Fix comment about targeted extension card. It was likely just c&p error.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/39e16e667aa8f132496092d4fa554935ddd5a55f.1606399500.git.michal.simek@xilinx.com

The commit f8f79fa6 ("dt-bindings: at25: convert the binding document
to yaml") converted binding to yaml and 3 deprecated properties pop up.

The patch is fixing these warnings:
.../zynq-zc770-xm013.dt.yaml: eeprom@2: 'pagesize' is a required property
.../zynq-zc770-xm013.dt.yaml: eeprom@2: 'size' is a required property
.../zynq-zc770-xm013.dt.yaml: eeprom@2: 'address-width' is a required property
>From schema: .../Documentation/devicetree/bindings/eeprom/at25.yaml

by converting them to new binding.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/be2c1125d98386033e182012eb08986924707a76.1606397101.git.michal.simek@xilinx.com

The commit f6962991 ("dt-bindings: sram: Convert SRAM bindings to
json-schema") converted binding to yaml and some missing required
properties started to be reported. Align binding based on it.

The patch is fixing these warnings:
.../zynq-zc702.dt.yaml: sram@fffc0000: '#address-cells' is a required property
.../zynq-zc702.dt.yaml: sram@fffc0000: '#size-cells' is a required property
.../zynq-zc702.dt.yaml: sram@fffc0000: 'ranges' is a required property
>From schema: .../Documentation/devicetree/bindings/sram/sram.yaml
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/87c02786ccd8d7827827a9d95a8737bb300caeb0.1606397101.git.michal.simek@xilinx.com

Fix the leds subnode names to match (^led-[0-9a-f]$|led).

Similar change has been also done by commit 9a19a39e ("arm64: dts:
zynqmp: Fix leds subnode name for zcu100/ultra96 v1").

The patch is fixing these warnings:
.../zynq-zc702.dt.yaml: leds: 'ds23' does not match any of the regexes:
'(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
>From schema: .../Documentation/devicetree/bindings/leds/leds-gpio.yaml
.../zynq-zybo-z7.dt.yaml: gpio-leds: 'ld4' does not match any of the
regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
>From schema: .../Documentation/devicetree/bindings/leds/leds-gpio.yaml
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/607a66783b129294364abf09a6fc8abd241ff4ee.1606397101.git.michal.simek@xilinx.com

Rename amba to AXI. Based on Xilinx Zynq TRM (Chapter 5) chip is "AXI
point-to-point channels for communicating addresses, data, and response
transactions between master and slave clients. This ARM AMBA 3.0..."

Issues are reported as:
.. amba: $nodename:0: 'amba' does not match
'^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
>From schema:
../github.com/devicetree-org/dt-schema/dtschema/schemas/simple-bus.yaml

Similar change has been done for Xilinx ZynqMP SoC.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/8a4bc80debfbb79c296e76fc1e4c173e62657286.1606397101.git.michal.simek@xilinx.com

The commit e359a292 ("dt-bindings: iio: accel: adxl345: switch to YAML
bindings") switched binding to yaml and the following error pop up:
../zynq-zturn-v5.dt.yaml: accelerometer@53: compatible: 'oneOf' conditional
failed, one must be
fixed:
['adi,adxl345', 'adxl345', 'adi,adxl34x', 'adxl34x'] is too long
Additional items are not allowed ('adi,adxl34x', 'adxl34x' were unexpected)
Additional items are not allowed ('adxl345', 'adi,adxl34x', 'adxl34x' were
unexpected)
'adi,adxl346' was expected
'adi,adxl345' was expected

Use only one compatible string to be aligned with the binding.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/a9075ab54df13461380e46d3002302d3672325b5.1606397101.git.michal.simek@xilinx.com

According to the datasheet (Rev. 1.9) the RTL8211F requires at least
72ms "for internal circuits settling time" before accessing the PHY
registers. On similar boards with the same PHY this fixes an issue where
Ethernet link would not come up when using ip link set down/up.

Fixes: a2c6e82e ("ARM: dts: meson: switch to the generic Ethernet PHY reset bindings")
Reviewed-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> # on Odroid-C1+
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/ff78772b306411e145769c46d4090554344db41e.1607363522.git.stefan@agner.ch

Add Aspeed AST2600 EDAC node into the common devicetree.
Signed-off-by: NTroy Lee <troy_lee@aspeedtech.com>
Signed-off-by: NBorislav Petkov <bp@suse.de>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Link: https://lkml.kernel.org/r/20201207090013.14145-2-troy_lee@aspeedtech.com

CAN0 and CAN1 instances share the same message ram configured
at 0x210000 on sama5d2 Linux systems.
According to current configuration of CAN0, we need 0x1c00 bytes
so that the CAN1 don't overlap its message ram:
64 x RX FIFO0 elements => 64 x 72 bytes
32 x TXE (TX Event FIFO) elements => 32 x 8 bytes
32 x TXB (TX Buffer) elements => 32 x 72 bytes
So a total of 7168 bytes (0x1C00).

Fix offset to match this needed size.
Make the CAN0 message ram ioremap match exactly this size so that is
easily understandable.  Adapt CAN1 size accordingly.

Fixes: bc6d5d76 ("ARM: dts: at91: sama5d2: add m_can nodes")
Reported-by: NDan Sneddon <dan.sneddon@microchip.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@bootlin.com>
Tested-by: NCristian Birsan <cristian.birsan@microchip.com>
Cc: stable@vger.kernel.org # v4.13+
Link: https://lore.kernel.org/r/20201203091949.9015-1-nicolas.ferre@microchip.com

Due to strobe signal not being propagated from CPU to securam
the securam needs to be mapped as device or strongly ordered memory
to work properly. Otherwise, updating to one offset may affect
the adjacent locations in securam.

Fixes: d4ce5f44 ("ARM: dts: at91: sama5d2: Add securam node")
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: NNicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/1606903025-14197-3-git-send-email-claudiu.beznea@microchip.com

atmel,osc-bypass property sets the bit 1 at main oscillator register.
On SAM9X60 this bit is not valid according to datasheet (chapter
28.16.9 PMC Clock Generator Main Oscillator Register).

Fixes: 1e5f532c ("ARM: dts: at91: sam9x60: add device tree for soc and board")
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: NNicolas Ferre <nicolas.ferre@microchip.com>
Cc: Marco Cardellini <marco.cardellini@microchip.com>
Link: https://lore.kernel.org/r/1606903025-14197-2-git-send-email-claudiu.beznea@microchip.com

Commit 2024b130 ("ARM: dts: exynos: Add Ethernet to Artik 5 board")
added ethernet chip on SPI0 bus and the whole bunch of assigned clock
entries to ensure proper clock rates and topology. Limit the assigned
clock parents only to the direct clocks of the SPI0 device and assume
that MPLL clock is already properly configured.

The applied clock topology was incorrect as some clocks between were
missing, what resulted in the following warning:

clk: failed to reparent div_mpll_pre to mout_mpll: -22

Fixes: 2024b130 ("ARM: dts: exynos: Add Ethernet to Artik 5 board")
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20201202122029.22198-1-m.szyprowski@samsung.comSigned-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

The SMDK6410 DTS was incorrectly called mini6410, probably copy-paste
from FriendlyARM Mini6410 board.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20201117201106.128813-4-krzk@kernel.org

Add a compatible for SMDK2416 board next to the SoC compatible.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20201117201106.128813-3-krzk@kernel.org