FIFO depth is configurable for each implementation of DW core,
so add a depth detection for those interface drivers who don't set
the fifo_len explicitly
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Acked-by: NJean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Section mismatch in reference from the function dw_spi_add_host()
to the function init_queue()
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Now dw_spi core fully supports 3 transfer modes: pure polling,
DMA and IRQ mode. IRQ mode will use the FIFO half empty as
the IRQ trigger, so each interface driver need set the fifo_len,
so that core driver can handle it properly
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Make the driver wait at least  for 1 jiffie before issuing the
warning, no matter what HZ is set to
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Driver for the Designware SPI core, it supports multipul interfaces like
PCI/APB etc.  User can use "dw_apb_ssi_db.pdf" from Synopsys as HW
datasheet.

[randy.dunlap@oracle.com: fix build]
[akpm@linux-foundation.org: build fix]
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: NRandy Dunlap <randy.dunlap@oracle.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>