1. 03 2月, 2017 9 次提交
    • J
      KVM: MIPS: Remove duplicated ASIDs from vcpu · c550d539
      James Hogan 提交于
      The kvm_vcpu_arch structure contains both mm_structs for allocating MMU
      contexts (primarily the ASID) but it also copies the resulting ASIDs
      into guest_{user,kernel}_asid[] arrays which are referenced from uasm
      generated code.
      
      This duplication doesn't seem to serve any purpose, and it gets in the
      way of generalising the ASID handling across guest kernel/user modes, so
      lets just extract the ASID straight out of the mm_struct on demand, and
      in fact there are convenient cpu_context() and cpu_asid() macros for
      doing so.
      
      To reduce the verbosity of this code we do also add kern_mm and user_mm
      local variables where the kernel and user mm_structs are used.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      c550d539
    • J
      KVM: MIPS/MMU: Move preempt/ASID handling to implementation · 1581ff3d
      James Hogan 提交于
      The MIPS KVM host and guest GVA ASIDs may need regenerating when
      scheduling a process in guest context, which is done from the
      kvm_arch_vcpu_load() / kvm_arch_vcpu_put() functions in mmu.c.
      
      However this is a fairly implementation specific detail. VZ for example
      may use GuestIDs instead of normal ASIDs to distinguish mappings
      belonging to different guests, and even on VZ without GuestID the root
      TLB will be used differently to trap & emulate.
      
      Trap & emulate GVA ASIDs only relate to the user part of the full
      address space, so can be left active during guest exit handling (guest
      context) to allow guest instructions to be easily read and translated.
      
      VZ root ASIDs however are for GPA mappings so can't be left active
      during normal kernel code. They also aren't useful for accessing guest
      virtual memory, and we should have CP0_BadInstr[P] registers available
      to provide encodings of trapping guest instructions anyway.
      
      Therefore move the ASID preemption handling into the implementation
      callback.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      1581ff3d
    • J
      KVM: MIPS: Convert get/set_regs -> vcpu_load/put · a60b8438
      James Hogan 提交于
      Convert the get_regs() and set_regs() callbacks to vcpu_load() and
      vcpu_put(), which provide a cpu argument and more closely match the
      kvm_arch_vcpu_load() / kvm_arch_vcpu_put() that they are called by.
      
      This is in preparation for moving ASID management into the
      implementations.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      a60b8438
    • J
      KVM: MIPS/MMU: Simplify ASID restoration · 1534b396
      James Hogan 提交于
      KVM T&E uses an ASID for guest kernel mode and an ASID for guest user
      mode. The current ASID is saved when the guest is scheduled out, and
      restored when scheduling back in, with checks for whether the ASID needs
      to be regenerated.
      
      This isn't really necessary as the ASID can be easily determined by the
      current guest mode, so lets simplify it to just read the required ASID
      from guest_kernel_asid or guest_user_asid even if the ASID hasn't been
      regenerated.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      1534b396
    • J
      KVM: MIPS: Drop partial KVM_NMI implementation · 00104b41
      James Hogan 提交于
      MIPS incompletely implements the KVM_NMI ioctl to supposedly perform a
      CPU reset, but all it actually does is invalidate the ASIDs. It doesn't
      expose the KVM_CAP_USER_NMI capability which is supposed to indicate the
      presence of the KVM_NMI ioctl, and no user software actually uses it on
      MIPS.
      
      Since this is dead code that would technically need updating for GVA
      page table handling in upcoming patches, remove it now. If we wanted to
      implement NMI injection later it can always be done properly along with
      the KVM_CAP_USER_NMI capability, and if we wanted to implement a proper
      CPU reset it would be better done with a separate ioctl.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      00104b41
    • J
      MIPS: Add return errors to protected cache ops · 7170bdc7
      James Hogan 提交于
      The protected cache ops contain no out of line fixup code to return an
      error code in the event of a fault, with the cache op being skipped in
      that case. For KVM however we'd like to detect this case as page
      faulting will be disabled so it could happen during normal operation if
      the GVA page tables were flushed, and need to be handled by the caller.
      
      Add the out-of-line fixup code to load the error value -EFAULT into the
      return variable, and adapt the protected cache line functions to pass
      the error back to the caller.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Acked-by: NRalf Baechle <ralf@linux-mips.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      7170bdc7
    • J
      MIPS: Export some tlbex internals for KVM to use · 722b4544
      James Hogan 提交于
      Export to TLB exception code generating functions so that KVM can
      construct a fast TLB refill handler for guest context without
      reinventing the wheel quite so much.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Acked-by: NRalf Baechle <ralf@linux-mips.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      722b4544
    • J
      MIPS: uasm: Add include guards in asm/uasm.h · 93a93c24
      James Hogan 提交于
      Add include guards in asm/uasm.h to allow it to be safely used by a new
      header asm/tlbex.h in the next patch to expose TLB exception building
      functions for KVM to use.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Acked-by: NRalf Baechle <ralf@linux-mips.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      93a93c24
    • J
      MIPS: Export pgd/pmd symbols for KVM · ccf01516
      James Hogan 提交于
      Export pmd_init(), invalid_pmd_table and tlbmiss_handler_setup_pgd to
      GPL kernel modules so that MIPS KVM can use the inline page table
      management functions and switch between page tables:
      
      - pmd_init() will be used directly by KVM to initialise newly allocated
        pmd tables with invalid lower level table pointers.
      
      - invalid_pmd_table is used by pud_present(), pud_none(), and
        pud_clear(), which KVM will use to test and clear pud entries.
      
      - tlbmiss_handler_setup_pgd() will be called by KVM entry code to switch
        to the appropriate GVA page tables.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Acked-by: NRalf Baechle <ralf@linux-mips.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      ccf01516
  2. 02 2月, 2017 2 次提交
  3. 05 1月, 2017 2 次提交
    • J
      KVM: MIPS: Flush KVM entry code from icache globally · 32eb12a6
      James Hogan 提交于
      Flush the KVM entry code from the icache on all CPUs, not just the one
      that built the entry code.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Cc: <stable@vger.kernel.org> # 3.16.x-
      Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com>
      32eb12a6
    • J
      KVM: MIPS: Don't clobber CP0_Status.UX · 4c881451
      James Hogan 提交于
      On 64-bit kernels, MIPS KVM will clear CP0_Status.UX to prevent the
      guest (running in user mode) from accessing the 64-bit memory segments.
      However the previous value of CP0_Status.UX is never restored when
      exiting from the guest.
      
      If the user process uses 64-bit addressing (the n64 ABI) this can result
      in address error exceptions from the kernel if it needs to deliver a
      signal before returning to user mode, as the kernel will need to write a
      sigframe to high user addresses on the user stack which are disallowed
      by CP0_Status.UX=0.
      
      This is fixed by explicitly setting SX and UX again when exiting from
      the guest, and explicitly clearing those bits when returning to the
      guest. Having the SX and UX bits set when handling guest exits (rather
      than only when exiting to userland) will be helpful when we support VZ,
      since we shouldn't need to directly read or write guest memory, so it
      will be valid for cache management IPIs to access host user addresses.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "Radim Krčmář" <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Cc: <stable@vger.kernel.org> # 4.8.x-
      Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com>
      4c881451
  4. 25 12月, 2016 3 次提交
  5. 15 12月, 2016 1 次提交
  6. 14 12月, 2016 1 次提交
  7. 11 12月, 2016 2 次提交
  8. 30 11月, 2016 1 次提交
    • F
      tcp: SOF_TIMESTAMPING_OPT_STATS option for SO_TIMESTAMPING · 1c885808
      Francis Yan 提交于
      This patch exports the sender chronograph stats via the socket
      SO_TIMESTAMPING channel. Currently we can instrument how long a
      particular application unit of data was queued in TCP by tracking
      SOF_TIMESTAMPING_TX_SOFTWARE and SOF_TIMESTAMPING_TX_SCHED. Having
      these sender chronograph stats exported simultaneously along with
      these timestamps allow further breaking down the various sender
      limitation.  For example, a video server can tell if a particular
      chunk of video on a connection takes a long time to deliver because
      TCP was experiencing small receive window. It is not possible to
      tell before this patch without packet traces.
      
      To prepare these stats, the user needs to set
      SOF_TIMESTAMPING_OPT_STATS and SOF_TIMESTAMPING_OPT_TSONLY flags
      while requesting other SOF_TIMESTAMPING TX timestamps. When the
      timestamps are available in the error queue, the stats are returned
      in a separate control message of type SCM_TIMESTAMPING_OPT_STATS,
      in a list of TLVs (struct nlattr) of types: TCP_NLA_BUSY_TIME,
      TCP_NLA_RWND_LIMITED, TCP_NLA_SNDBUF_LIMITED. Unit is microsecond.
      Signed-off-by: NFrancis Yan <francisyyan@gmail.com>
      Signed-off-by: NYuchung Cheng <ycheng@google.com>
      Signed-off-by: NSoheil Hassas Yeganeh <soheil@google.com>
      Acked-by: NNeal Cardwell <ncardwell@google.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      1c885808
  9. 25 11月, 2016 1 次提交
  10. 24 11月, 2016 1 次提交
    • P
      MIPS: Mask out limit field when calculating wired entry count · 10313980
      Paul Burton 提交于
      Since MIPSr6 the Wired register is split into 2 fields, with the upper
      16 bits of the register indicating a limit on the value that the wired
      entry count in the bottom 16 bits of the register can take. This means
      that simply reading the wired register doesn't get us a valid TLB entry
      index any longer, and we instead need to retrieve only the lower 16 bits
      of the register. Introduce a new num_wired_entries() function which does
      this on MIPSr6 or higher and simply returns the value of the wired
      register on older architecture revisions, and make use of it when
      reading the number of wired entries.
      
      Since commit e710d666 ("MIPS: tlb-r4k: If there are wired entries,
      don't use TLBINVF") we have been using a non-zero number of wired
      entries to determine whether we should avoid use of the tlbinvf
      instruction (which would invalidate wired entries) and instead loop over
      TLB entries in local_flush_tlb_all(). This loop begins with the number
      of wired entries, or before this patch some large bogus TLB index on
      MIPSr6 systems. Thus since the aforementioned commit some MIPSr6 systems
      with FTLBs have been prone to leaving stale address translations in the
      FTLB & crashing in various weird & wonderful ways when we later observe
      the wrong memory.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: Matt Redfearn <matt.redfearn@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/14557/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      10313980
  11. 23 11月, 2016 1 次提交
    • E
      ptrace: Don't allow accessing an undumpable mm · 84d77d3f
      Eric W. Biederman 提交于
      It is the reasonable expectation that if an executable file is not
      readable there will be no way for a user without special privileges to
      read the file.  This is enforced in ptrace_attach but if ptrace
      is already attached before exec there is no enforcement for read-only
      executables.
      
      As the only way to read such an mm is through access_process_vm
      spin a variant called ptrace_access_vm that will fail if the
      target process is not being ptraced by the current process, or
      the current process did not have sufficient privileges when ptracing
      began to read the target processes mm.
      
      In the ptrace implementations replace access_process_vm by
      ptrace_access_vm.  There remain several ptrace sites that still use
      access_process_vm as they are reading the target executables
      instructions (for kernel consumption) or register stacks.  As such it
      does not appear necessary to add a permission check to those calls.
      
      This bug has always existed in Linux.
      
      Fixes: v1.0
      Cc: stable@vger.kernel.org
      Reported-by: NAndy Lutomirski <luto@amacapital.net>
      Signed-off-by: N"Eric W. Biederman" <ebiederm@xmission.com>
      84d77d3f
  12. 17 11月, 2016 1 次提交
  13. 16 11月, 2016 2 次提交
    • C
      locking/core, arch: Remove cpu_relax_lowlatency() · 5bd0b85b
      Christian Borntraeger 提交于
      As there are no users left, we can remove cpu_relax_lowlatency()
      implementations from every architecture.
      Signed-off-by: NChristian Borntraeger <borntraeger@de.ibm.com>
      Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Nicholas Piggin <npiggin@gmail.com>
      Cc: Noam Camus <noamc@ezchip.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Russell King <linux@armlinux.org.uk>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: linuxppc-dev@lists.ozlabs.org
      Cc: virtualization@lists.linux-foundation.org
      Cc: xen-devel@lists.xenproject.org
      Cc: <linux-arch@vger.kernel.org>
      Link: http://lkml.kernel.org/r/1477386195-32736-6-git-send-email-borntraeger@de.ibm.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
      5bd0b85b
    • C
      locking/core: Introduce cpu_relax_yield() · 79ab11cd
      Christian Borntraeger 提交于
      For spinning loops people do often use barrier() or cpu_relax().
      For most architectures cpu_relax and barrier are the same, but on
      some architectures cpu_relax can add some latency.
      For example on power,sparc64 and arc, cpu_relax can shift the CPU
      towards other hardware threads in an SMT environment.
      On s390 cpu_relax does even more, it uses an hypercall to the
      hypervisor to give up the timeslice.
      In contrast to the SMT yielding this can result in larger latencies.
      In some places this latency is unwanted, so another variant
      "cpu_relax_lowlatency" was introduced. Before this is used in more
      and more places, lets revert the logic and provide a cpu_relax_yield
      that can be called in places where yielding is more important than
      latency. By default this is the same as cpu_relax on all architectures.
      Signed-off-by: NChristian Borntraeger <borntraeger@de.ibm.com>
      Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Nicholas Piggin <npiggin@gmail.com>
      Cc: Noam Camus <noamc@ezchip.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Russell King <linux@armlinux.org.uk>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: linuxppc-dev@lists.ozlabs.org
      Cc: virtualization@lists.linux-foundation.org
      Cc: xen-devel@lists.xenproject.org
      Link: http://lkml.kernel.org/r/1477386195-32736-2-git-send-email-borntraeger@de.ibm.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
      79ab11cd
  14. 05 11月, 2016 3 次提交
  15. 04 11月, 2016 10 次提交
    • J
      MIPS: Fix max_low_pfn with disabled highmem · 16a767ec
      James Hogan 提交于
      When low memory doesn't reach HIGHMEM_START (e.g. up to 256MB at PA=0 is
      common) and highmem is present above HIGHMEM_START (e.g. on Malta the
      RAM overlayed by the IO region is aliased at PA=0x90000000), max_low_pfn
      will be initially calculated very large and then clipped down to
      HIGHMEM_START.
      
      This causes crashes when reading /sys/kernel/mm/page_idle/bitmap
      (i.e. CONFIG_IDLE_PAGE_TRACKING=y) when highmem is disabled. pfn_valid()
      will compare against max_mapnr which is derived from max_low_pfn when
      there is no highend_pfn set up, and will return true for PFNs right up
      to HIGHMEM_START, even though they are beyond the end of low memory and
      no page structs will actually exist for these PFNs.
      
      This is fixed by skipping high memory regions when initially calculating
      max_low_pfn if highmem is disabled, so it doesn't get clipped too high.
      We also clip regions which overlap the highmem boundary when highmem is
      disabled, so that max_pfn doesn't extend into highmem either.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/14490/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      16a767ec
    • M
      MIPS: Correct MIPS I FP sigcontext layout · f92722dc
      Maciej W. Rozycki 提交于
      Complement commit 80cbfad7 ("MIPS: Correct MIPS I FP context
      layout") and correct the way Floating Point General registers are stored
      in a signal context with MIPS I hardware.
      
      Use the S.D and L.D assembly macros to have pairs of SWC1 instructions
      and pairs of LWC1 instructions produced, respectively, in an arrangement
      which makes the memory representation of floating-point data passed
      compatible with that used by hardware SDC1 and LDC1 instructions, where
      available, regardless of the hardware endianness used.  This matches the
      layout used by r4k_fpu.S, ensuring run-time compatibility for MIPS I
      software across all o32 hardware platforms.
      
      Define an EX2 macro to handle exceptions from both hardware instructions
      implicitly produced from S.D and L.D assembly macros.
      Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/14477/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      f92722dc
    • M
      MIPS: Fix ISA I/II FP signal context offsets · 758ef0a9
      Maciej W. Rozycki 提交于
      Fix a regression introduced with commit 2db9ca0a ("MIPS: Use struct
      mips_abi offsets to save FP context") for MIPS I/I FP signal contexts,
      by converting save/restore code to the updated internal API.  Start FGR
      offsets from 0 rather than SC_FPREGS from $a0 and use $a1 rather than
      the offset of SC_FPC_CSR from $a0 for the Floating Point Control/Status
      Register (FCSR).
      
      Document the new internal API and adjust assembly code formatting for
      consistency.
      Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/14476/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      758ef0a9
    • M
      MIPS: Remove FIR from ISA I FP signal context · 6daaa326
      Maciej W. Rozycki 提交于
      Complement commit e50c0a8f ("Support the MIPS32 / MIPS64 DSP ASE.")
      and remove the Floating Point Implementation Register (FIR) from the FP
      register set recorded in a signal context with MIPS I processors too, in
      line with the change applied to r4k_fpu.S.
      
      The `sc_fpc_eir' slot is unused according to our current ABI and the FIR
      register is read-only and always directly accessible from user software.
      
      [ralf@linux-mips.org: This is also required because the next commit depends
      on it.]
      Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/14475/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      6daaa326
    • M
      MIPS: Fix ISA I FP sigcontext access violation handling · 35938a00
      Maciej W. Rozycki 提交于
      Complement commit 0ae8dceaebe3 ("Merge with 2.3.10.") and use the local
      `fault' handler to recover from FP sigcontext access violation faults,
      like corresponding code does in r4k_fpu.S.  The `bad_stack' handler is
      in syscall.c and is not suitable here as we want to propagate the error
      condition up through the caller rather than killing the thread outright.
      Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/14474/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      35938a00
    • M
      MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue · 5a1aca44
      Maciej W. Rozycki 提交于
      Sanitize FCSR Cause bit handling, following a trail of past attempts:
      
      * commit 42495484 ("MIPS: ptrace: Fix FP context restoration FCSR
      regression"),
      
      * commit 443c4403 ("MIPS: Always clear FCSR cause bits after
      emulation"),
      
      * commit 64bedffe ("MIPS: Clear [MSA]FPE CSR.Cause after
      notify_die()"),
      
      * commit b1442d39 ("MIPS: Prevent user from setting FCSR cause
      bits"),
      
      * commit b54d2901517d ("Properly handle branch delay slots in connection
      with signals.").
      
      Specifically do not mask these bits out in ptrace(2) processing and send
      a SIGFPE signal instead whenever a matching pair of an FCSR Cause and
      Enable bit is seen as execution of an affected context is about to
      resume.  Only then clear Cause bits, and even then do not clear any bits
      that are set but masked with the respective Enable bits.  Adjust Cause
      bit clearing throughout code likewise, except within the FPU emulator
      proper where they are set according to IEEE 754 exceptions raised as the
      operation emulated executed.  Do so so that any IEEE 754 exceptions
      subject to their default handling are recorded like with operations
      executed by FPU hardware.
      Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/14460/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      5a1aca44
    • M
      MIPS: ptrace: Also initialize the FP context on individual FCSR writes · c9e56039
      Maciej W. Rozycki 提交于
      Complement commit ac9ad83b ("MIPS: prevent FP context set via ptrace
      being discarded") and also initialize the FP context whenever FCSR alone
      is written with a PTRACE_POKEUSR request addressing FPC_CSR, rather than
      along with the full FPU register set in the case of the PTRACE_SETFPREGS
      request.
      Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/14459/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      c9e56039
    • J
      MIPS: dump_tlb: Fix printk continuations · 8a98495c
      James Hogan 提交于
      Since commit 4bcc595c ("printk: reinstate KERN_CONT for printing
      continuation lines") the output from TLB dumps on MIPS has been
      pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to
      provide the appropriate markers & restore the expected output.
      
      Continuation is also used for the second line of each TLB entry printed
      in dump_tlb.c even though it has a newline, since it is a continuation
      of the interpretation of the same TLB entry. For example:
      
      [   46.371884] Index:  0 pgmask=16kb va=77654000 asid=73 gid=00
              [ri=0 xi=0 pa=ffc18000 c=5 d=0 v=1 g=0] [ri=0 xi=0 pa=ffc1c000 c=5 d=0 v=1 g=0]
      [   46.385380] Index: 12 pgmask=16kb va=004b4000 asid=73 gid=00
              [ri=0 xi=0 pa=00000000 c=0 d=0 v=0 g=0] [ri=0 xi=0 pa=ffb00000 c=5 d=1 v=1 g=0]
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Maciej W. Rozycki <macro@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/14444/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      8a98495c
    • P
      MIPS: Fix __show_regs() output · 752f5499
      Paul Burton 提交于
      Since commit 4bcc595c ("printk: reinstate KERN_CONT for printing
      continuation lines") the output from __show_regs() on MIPS has been
      pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to
      provide the appropriate markers & restore the expected register output.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Signed-off-by: NMatt Redfearn <matt.redfearn@imgtec.com>
      Cc: Maciej W. Rozycki <macro@imgtec.com>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/14432/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      752f5499
    • M
      MIPS: traps: Fix output of show_code · 41000c58
      Matt Redfearn 提交于
      Since commit 4bcc595c ("printk: reinstate KERN_CONT for printing
      continuation lines") the output from show_code on MIPS has been
      pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to
      provide the appropriate markers & restore the expected output.
      Signed-off-by: NMatt Redfearn <matt.redfearn@imgtec.com>
      Cc: Maciej W. Rozycki <macro@imgtec.com>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/14431/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      41000c58
反馈
建议
客服 返回
顶部