1. 30 7月, 2017 1 次提交
  2. 10 2月, 2017 2 次提交
  3. 09 2月, 2017 1 次提交
  4. 06 2月, 2017 1 次提交
    • I
      serial: 8250_pci: Add MKS Tenta SCOM-0800 and SCOM-0801 cards · 1c9c858e
      Ian Abbott 提交于
      The MKS Instruments SCOM-0800 and SCOM-0801 cards (originally by Tenta
      Technologies) are 3U CompactPCI serial cards with 4 and 8 serial ports,
      respectively.  The first 4 ports are implemented by an OX16PCI954 chip,
      and the second 4 ports are implemented by an OX16C954 chip on a local
      bus, bridged by the second PCI function of the OX16PCI954.  The ports
      are jumper-selectable as RS-232 and RS-422/485, and the UARTs use a
      non-standard oscillator frequency of 20 MHz (base_baud = 1250000).
      Signed-off-by: NIan Abbott <abbotti@mev.co.uk>
      Cc: stable <stable@vger.kernel.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      1c9c858e
  5. 03 2月, 2017 1 次提交
  6. 12 1月, 2017 1 次提交
  7. 11 1月, 2017 1 次提交
  8. 30 11月, 2016 1 次提交
    • G
      serial: 8250_pci: Detach low-level driver during PCI error recovery · f209fa03
      Gabriel Krisman Bertazi 提交于
      During a PCI error recovery, like the ones provoked by EEH in the ppc64
      platform, all IO to the device must be blocked while the recovery is
      completed.  Current 8250_pci implementation only suspends the port
      instead of detaching it, which doesn't prevent incoming accesses like
      TIOCMGET and TIOCMSET calls from reaching the device.  Those end up
      racing with the EEH recovery, crashing it.  Similar races were also
      observed when opening the device and when shutting it down during
      recovery.
      
      This patch implements a more robust IO blockage for the 8250_pci
      recovery by unregistering the port at the beginning of the procedure and
      re-adding it afterwards.  Since the port is detached from the uart
      layer, we can be sure that no request will make through to the device
      during recovery.  This is similar to the solution used by the JSM serial
      driver.
      
      I thank Peter Hurley <peter@hurleysoftware.com> for valuable input on
      this one over one year ago.
      Signed-off-by: NGabriel Krisman Bertazi <krisman@linux.vnet.ibm.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      f209fa03
  9. 10 11月, 2016 1 次提交
    • A
      8250: FIX Fourth port offset of Pericom PI7C9X7954 boards · 5c31ef91
      Angelo Butti 提交于
      Hi,
      below patch to fix Fourth port offset of Percom PI7C9X7954 boards.
      
      I had a problem using Fourth port on a pci express serial board based on Pericom
      PI7C9X7954. Reading datasheet I notice a "special" offset assign to this port
      when used in I/O mode.
      
      Offset 0x0 ->  UART 0
      Offset 0x8 ->  UART 1
      Offset 0x10 ->  UART 2
      Offset 0x38 ->  UART 3  <<---- This don't follow a logical sequence
      
      This patch add a different init to last port, to have right offset.
      
      I check also Pericom 7952 and 7958 but that devices follow logical sequence,
      so they are ok.
      
      Regards,
      Angelo
      Signed-off-by: NAngelo Butti <buttiangelo@gmail.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      5c31ef91
  10. 22 9月, 2016 1 次提交
  11. 31 8月, 2016 3 次提交
  12. 26 6月, 2016 2 次提交
  13. 01 5月, 2016 1 次提交
  14. 29 4月, 2016 1 次提交
  15. 14 4月, 2016 1 次提交
    • A
      dmaengine: dw: rename masters to reflect actual topology · c422025c
      Andy Shevchenko 提交于
      The source and destination masters are reflecting buses or their layers to
      where the different devices can be connected. The patch changes the master
      names to reflect which one is related to which independently on the transfer
      direction.
      
      The outcome of the change is that the memory data width is now always limited
      by a data width of the master which is dedicated to communicate to memory.
      
      The patch will not break anything since all current users have the same data
      width for all masters. Though it would be nice to revisit avr32 platforms to
      check what is the actual hardware topology in use there. It seems that it has
      one bus and two masters on it as stated by Table 8-2, that's why everything
      works independently on the master in use. The purpose of the sequential patch
      is to fix the driver for configuration of more than one bus.
      
      The change is done in the assumption that src_master and dst_master are
      reflecting a connection to the memory and peripheral correspondently on avr32
      and otherwise on the rest.
      Acked-by: NHans-Christian Egtvedt <egtvedt@samfundet.no>
      Acked-by: NMark Brown <broonie@kernel.org>
      Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
      Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      c422025c
  16. 08 3月, 2016 3 次提交
  17. 07 2月, 2016 9 次提交
  18. 30 1月, 2016 1 次提交
  19. 18 10月, 2015 2 次提交
  20. 06 8月, 2015 1 次提交
    • P
      serial: 8250_pci: fix mode after S3/S4 resume for F81504/508/512 · d3159455
      Peter Hung 提交于
      Fix RS232/485 mode incorrect setting after S3/S4 resume for F81504/508/512
      
      We had add RS232/485 RTS control with fecf27a3. But when it
      resume from S3/S4, the mode register 0x40 + 0x08 * idx + 7 will
      rewrite to 0x01 (RS232 mode).
      
      This patch will modify 2 sections.
      
      One is pci_fintek_init(), if it called when first init, it will
      write mode register with 0x01. If it called from S3/S4 resume,
      it's will get the relative port data and pass it to
      pci_fintek_rs485_config() with NULL rs485 parameter.
      
      The another modification is in pci_fintek_rs485_config(). It'll
      re-apply old configuration when the parameter rs485 is NULL.
      Signed-off-by: NPeter Hung <hpeter+linux_kernel@gmail.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      d3159455
  21. 05 8月, 2015 2 次提交
  22. 04 8月, 2015 1 次提交
    • P
      serial: 8250_pci: add RS485 for F81504/508/512 · fecf27a3
      Peter Hung 提交于
      Add RS485 control for Fintek F81504/508/512
      
      F81504/508/512 can control their RTS with H/W mode.
      PCI configuration space for each port is 0x40 + idx * 8 + 7.
      
      When it set with 0x01, it's configured with RS232 mode.
      RTS is controlled by MCR.
      
      When it set with 0x11, it's configured with RS485 mode.
      RTS is controlled by H/W, RTS low with idle & RX, high with TX.
      
      When it set with 0x31, it's configured with RS485 mode.
      RTS is controlled by H/W, RTS high with idle & RX, low with TX.
      
      We will force 0x01 on pci_fintek_setup().
      Signed-off-by: NPeter Hung <hpeter+linux_kernel@gmail.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      fecf27a3
  23. 13 6月, 2015 2 次提交