Signed-off-by: NJose Alberto Reguero <jareguero@telefonica.net>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Under certain circumstances (SSP turned off by the BIOS) and for
debugging purposes, skipping global controller reset is helpful.  Add
a kernel parameter for it.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

ahci is often implemented with accompanying SFF compatible interface
and legacy IDE driver may attach to the legacy IO ports when the
controller is already claimed by ahci and vice-versa.  This patch
makes ahci use pcim_iomap_regions_request_all() so that all IO regions
are claimed on attach.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

logical-bitwise & confusion
Signed-off-by: NRoel Kluin <12o3l@tiscali.nl>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Signed-off-by: NPeer Chen <peerchen@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

This addresses the recent ATI SB600 errata, where the hardware does
not like 256-length PRD entries during FPDMA (aka NCQ).

It hurts performance on SB600, but it is more important to get a
correct patch eliminating the data corruption/lockups, and then later
on tune for performance.

We simply limit each command to a maximum of 255 sectors, on SB600.
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

SB700 SATA controller can support 64 bit DMA, the previous commit
badc2341 was added with
careless reference to SB600, which should be modified by this patch.
Signed-off-by: NShane Huang <shane.huang@amd.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

During the last step of hibernation in the "platform" mode (with the
help of ACPI) we use the suspend code, including the devices'
->suspend() methods, to prepare the system for entering the ACPI S4
system sleep state.

But at least for some devices the operations performed by the
->suspend() callback in that case must be different from its operations
during regular suspend.

For this reason, introduce the new PM event type PM_EVENT_HIBERNATE and
pass it to the device drivers' ->suspend() methods during the last phase
of hibernation, so that they can distinguish this case and handle it as
appropriate.  Modify the drivers that handle PM_EVENT_SUSPEND in a
special way and need to handle PM_EVENT_HIBERNATE in the same way.

These changes are necessary to fix a hibernation regression related
to the i915 driver (ref. http://lkml.org/lkml/2008/2/22/488).
Signed-off-by: NRafael J. Wysocki <rjw@sisk.pl>
Acked-by: NPavel Machek <pavel@ucw.cz>
Tested-by: NJeff Chua <jeff.chua.linux@gmail.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

that provided by the block layer

ATA requires that all DMA transfers begin and end on word boundaries.
Because of this, a large amount of machinery grew up in ide to adjust
scatterlists on this basis.  However, as of 2.5, the block layer has a
dma_alignment variable which ensures both the beginning and length of a
DMA transfer are aligned on the dma_alignment boundary.  Although the
block layer does adjust the beginning of the transfer to ensure this
happens, it doesn't actually adjust the length, it merely makes sure
that space is allocated for transfers beyond the declared length.  The
upshot of this is that scatterlists may be padded to any size between
the actual length and the length adjusted to the dma_alignment safely
knowing that memory is allocated in this region.

Right at the moment, SCSI takes the default dma_aligment which is on a
512 byte boundary.  Note that this aligment only applies to transfers
coming in from user space.  However, since all kernel allocations are
automatically aligned on a minimum of 32 byte boundaries, it is safe to
adjust them in this manner as well.

tj: * Adjusting sg after padding is done in block layer.  Make libata
      set queue alignment correctly for ATAPI devices and drop broken
      sg mangling from ata_sg_setup().
    * Use request->raw_data_len for ATAPI transfer chunk size.
    * Killed qc->raw_nbytes.
    * Separated out killing qc->n_iter.
Signed-off-by: NJames Bottomley <James.Bottomley@HansenPartnership.com>
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJens Axboe <jens.axboe@oracle.com>

AHCI uses CAP.NP to indicate the number of ports and PI to tell which
ports are enabled.  The only requirement is that the number of ports
indicated by CAP.NP should equal or be higher than the number of
enabled ports in PI.

CAP.NP and PI carry duplicate information and there have been some
interesting cases.  Some early AHCI controllers didn't set PI at all
and just implement from port 0 to CAP.NP.  An ICH8 board which wired
four out of six available ports had 3 (4 ports) for CAP.NP and 0x33
for PI.  While ESB2 has less bits set in PI than the value in CAP.NP.

Till now, ahci driver assumed that PI is invalid if it doesn't match
CAP.NP exactly.  This violates AHCI standard and the driver ends up
accessing unmimplemented ports on ESB2.

This patch updates CAP.NP and PI handling such that PI can have less
number of bits set than indicated in CAP.NP and the highest port is
determined as the maximum port of what CAP.NP and PI indicate.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Cc: Jan Beulich <jbeulich@novell.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

This patch adds the Intel ICH10 SATA RAID Controllers DeviceID's.
Signed-off-by: NJason Gaston <jason.d.gaston@intel.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Factor out AHCI enabling into ahci_enable_ahci() and enabling AHCI
before reading CAP in ahci_save_initial_config() as the spec requires
enabling AHCI mode before accessing any other registers.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

libata used private sg iterator to handle padding sg.  Now that sg can
be chained, padding can be handled using standard sg ops.  Convert to
chained sg.

* s/qc->__sg/qc->sg/

* s/qc->pad_sgent/qc->extra_sg[]/.  Because chaining consumes one sg
  entry.  There need to be two extra sg entries.  The renaming is also
  for future addition of other extra sg entries.

* Padding setup is moved into ata_sg_setup_extra() which is organized
  in a way that future addition of other extra sg entries is easy.

* qc->orig_n_elem is unused and removed.

* qc->n_elem now contains the number of sg entries that LLDs should
  map.  qc->mapped_n_elem is added to carry the original number of
  mapped sgs for unmapping.

* The last sg of the original sg list is used to chain to extra sg
  list.  The original last sg is pointed to by qc->last_sg and the
  content is stored in qc->saved_last_sg.  It's restored during
  ata_sg_clean().

* All sg walking code has been updated.  Unnecessary assertions and
  checks for conditions the core layer already guarantees are removed.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Cc: Jens Axboe <jens.axboe@oracle.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Implement protocol tests - ata_is_atapi(), ata_is_nodata(),
ata_is_pio(), ata_is_dma(), ata_is_ncq() and ata_is_data() and use
them to replace is_atapi_taskfile() and hard coded protocol tests.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

For intel ones, ahci unconditionally OR'd 0xf to PCS.  This isn't
correct for the following cases.

* ich6/7m's which only implement P0 and P2 (0xf works fine tho)

* ich8/9's which have six ports and needs 0x3f to enable all ports

This patch updates PCS programming such that...

* port_map determined by ahci_save_initial_config() is OR'd instead of 0xf

* PCS is updated only if necessary (there are turned off enable bits)

port_map is determined from PORTS_IMPL PCI register which is
implemented as write or write-once register.  If the register isn't
programmed, ahci automatically generates it from number of ports,
which is good enough for PCS programming.  ICH6/7M are probably the
only ones where non-contiguous enable bits are necessary && PORTS_IMPL
isn't programmed properly but they're proven to work reliably with 0xf
anyway.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Spurious NCQ completion detection implemented in ahci was incorrect.
On AHCI receving and processing FISes and raising interrupts are not
interlocked and spurious interrupts are expected.

For example, if an interrupt occurs while interrupt handler is running
and the running interrupt handler handles the event the new IRQ
indicated, after IRQ handler finishes, it will be executed again
because IRQ pending bit is set by the new interrupt but there won't be
anything to process.

Please read the following message for more information.

  http://article.gmane.org/gmane.linux.ide/26012

This patch...

* Removes all spurious IRQ whining from ahci.  Spurious NCQ completion
  detection was completely wrong.  Spurious D2H Register FIS taught us
  that some early drives send spurious D2H Register FIS with I bit set
  while NCQ commands are in progress but none of recent drives does
  that and even the ones which show such behavior can do NCQ fine.

* Kills all NCQ blacklist entries which were added because of spurious
  NCQ completions.  I tracked down each commit and verified all
  removed ones are actually added because of spurious completions.

  WD740ADFD-00NLR1 wasn't deleted but moved upward because the drive
  not only had spurious NCQ completions but also is slow on sequential
  data transfers if NCQ is enabled.

  Maxtor 7V300F0 was added by 0e3dbc01
  from Alan Cox.  I can only find evidences that the drive only had
  troubles with spuruious completions by searching the mailing list.
  This entry needs to be verified and removed if it doesn't have other
  NCQ related problems.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

ICH6 R/Ms share PCI ID between piix and ahci modes and we've been
allowing ahci to attach regardless of how BIOS configured it.
However, enabling AHCI mode when the controller is in combined mode
can result in unexpected behavior.  Don't attach if the controller is
in combined mode.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Cc: Bill Nottingham <notting@redhat.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

There isn't much point in reporting -EOPNOTSUPP as failure.  Also the
message was missing newline.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Add the device IDs of legacy mode of MCP79 AHCI controller to ahci.c
Signed-off-by: NPeer Chen <peerchen@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

This patch will set the correct bits to turn on Aggressive
Link Power Management (ALPM) for the ahci driver.  This
will cause the controller and disk to negotiate a lower
power state for the link when there is no activity (see
the AHCI 1.x spec for details).  This feature is mutually
exclusive with Hot Plug, so when ALPM is enabled, Hot Plug
is disabled.  ALPM will be enabled by default, but it is
settable via the scsi host syfs interface.  Possible
settings for this feature are:

Setting         Effect
----------------------------------------------------------
min_power       ALPM is enabled, and link set to enter
                lowest power state (SLUMBER) when idle
                Hot plug not allowed.

max_performance ALPM is disabled, Hot Plug is allowed

medium_power    ALPM is enabled, and link set to enter
                second lowest power state (PARTIAL) when
                idle.  Hot plug not allowed.
Signed-off-by: NKristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

The recent fix to host reset introduced a problem, whereby AHCI-enable
bit would be cleared upon reset, if it was not asserted prior to reset.

Unconditionally enable AHCI-enable bit.
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

On certain device/controller combination, 0xff status is asserted
after reset and doesn't get cleared during 150ms post-reset wait.  As
0xff status is interpreted as no device (for good reasons), this can
lead to misdetection on such cases.

This patch implements ata_wait_after_reset() which replaces the 150ms
sleep and waits upto ATA_TMOUT_FF_WAIT if status is 0xff.
ATA_TMOUT_FF_WAIT is currently 800ms which is enough for
HHD424020F7SV00 to get detected but not enough for Quantum GoVault
drive which is known to take upto 2s.

Without parallel probing, spending 2s on 0xff port would incur too
much delay on ata_piix's which use 0xff to indicate empty port and
doesn't have SCR register, so GoVault needs to wait till parallel
probing.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

P5W-DH Deluxe has ICH9 which doesn't have PMP support but SIMG 4726
hardwired to the second port of AHCI controller at PCI device 1f.2.
The 4726 doesn't work as PMP but as a storage processor which can do
hardware RAID on downstream ports.

When no device is attached to the downstream port of the 4726, pseudo
ATA device for configuration appears.  Unfortunately, ATA emulation on
the device is very lousy and causes long hang during boot.

This patch implements workaround for the board.  If the mainboard is
P5W-DH Deluxe (matched using DMI), only hardreset is used on the
second port of AHCI controller @ 1f.2 and the hardreset doesn't depend
on receiving the first FIS and just proceed to IDENTIFY.

This workaround fixes bugzilla #8923.

  http://bugzilla.kernel.org/show_bug.cgi?id=8923Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Tackle the relatively sane complaints of checkpatch --file.

The vast majority is indentation and whitespace changes, the rest are

* #include fixes
* printk KERN_xxx prefix addition
* BSS/initializer cleanups
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

Fix the various misspellings of "system", controller", "interrupt" and
"[un]necessary".
Signed-off-by: NRobert P. J. Day <rpjday@mindspring.com>
Signed-off-by: NAdrian Bunk <bunk@kernel.org>

PMP registers used to be accessed with dedicated accessors ->pmp_read
and ->pmp_write.  During reset, those callbacks are called with the
port frozen so they should be able to run without depending on
interrupt delivery.  To achieve this, they were implemented polling.

However, as resetting the host port makes the PMP to isolate fan-out
ports until SError.X is cleared, resetting fan-out ports while port is
frozen doesn't buy much additional safety.

This patch updates libata PMP support such that PMP registers are
accessed using regular ata_exec_internal() mechanism and kills
->pmp_read/write() callbacks.  The following changes are made.

* PMP access helpers - sata_pmp_read_init_tf(), sata_pmp_read_val(),
  sata_pmp_write_init_tf() are folded into sata_pmp_read/write() which
  are now standalone PMP register access functions.

* sata_pmp_read/write() returns err_mask instead of rc.  This is
  consistent with other functions which issue internal commands and
  allows more detailed error reporting.

* ahci interrupt handler is modified to ignore BAD_PMP and
  spurious/illegal completion IRQs while reset is in progress.  These
  conditions are expected during reset.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Asynchronous notification on ICH9 didn't work because it didn't write
AN FIS into the RX area - it only updates SNotification.  Also,
snooping SDB_FIS RX area is racy against further SDB FIS receptions.
Let sata_async_notification() determine using SNTF if it's available
and snoop RX area iff SNTF isn't available
Signed-off-by: NTejun Heo <htejun@gmail.com>
Cc: Kristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Now that we have pp->intr_mask, move PORT_IRQ_BAD_PMP enabling to
ahci_pmp_attach/detach() where it belongs.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

ahci had problems with NCQ over PMP and NCQ used to be disabled while
PMP was attached.  After fixing the problem, the temporary NCQ
disabling code wasn't removed completely.  Kill the remaining piece.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Signed-off-by: NPeer Chen <peerchen@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Of course some controllers lie about PMP support.  Black list them.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Private pi.flags area is full and we need more private flags.  Move
host private flags over to pi.private_data.  During initialization,
these flags are copied to hpriv->flags.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Implement AHCI PMP support.  ahci only supports command based
switching.  Also, for some reason, NCQ over PMP doesn't work now.
Other than that, everything works.

Tested on ICH9R, JMB360/363 + SIMG3726, 4726 and 5744.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Cc: Forrest Zhao <forrest.zhao@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

AHCI spec says host-reset bit may only be set when the ahci-enable bit
is also set.

Noticed by Peer Chen <peerchen@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

AN serves multiple purposes.  For ATAPI, it's used for media change
notification.  For PMP, for downstream PHY status change notification.
Implement sata_async_notification() which demultiplexes AN.

To avoid unnecessary port events, ATAPI AN is not enabled if PMP is
attached but SNTF is not available.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Cc: Kriten Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Controllers which support PMP have various restrictions on which
combinations of commands are allowed to what number of devices
concurrently.  This patch implements ops->qc_defer() which determines
whether a qc can be issued at the moment or should be deferred.

If the function returns ATA_DEFER_LINK, the qc will be deferred until
a qc completes on the link.  If ATA_DEFER_PORT, until a qc completes
on any link.  The defer conditions are advisory and in general
ATA_DEFER_LINK can be considered as lower priority deferring than
ATA_DEFER_PORT.

ops->qc_defer() replaces fixed ata_scmd_need_defer().  For standard
NCQ/non-NCQ exclusion, ata_std_qc_defer() is implemented.  ahci and
sata_sil24 are converted to use ata_std_qc_defer().

ops->qc_defer() is heavier than the original mechanism because full qc
is prepped before determining to defer it, but various information is
needed to determine defer conditinos and fully translating a qc is the
only way to supply such information in generic manner.

IMHO, this shouldn't cause any noticeable performance issues as

* for most cases deferring occurs rarely (except for NCQ-aware
  cmd-switching PMP)
* translation itself isn't that expensive
* once deferred the command won't be repeated until another command
  completes which usually is a very long time cpu-wise.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Update AN support in preparation of PMP support.

* s/ata_id_has_AN/ata_id_has_atapi_AN/
* add AN enabled reporting during configuration
* add err_mask to AN configuration failure reporting
* update LOCKING comment for ata_scsi_media_change_notify()
* check whether ATA dev is attached to SCSI dev ata_scsi_media_change_notify()
* set ATA_FLAG_AN in ahci and sata_sil24
Signed-off-by: NTejun Heo <htejun@gmail.com>
Cc: Kriten Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Signed-off-by: NJason Gaston <jason.d.gaston@intel.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Reimplement port_map handling such that

1. Non-zero PORTS_IMPL value is always examined and used if consistent
   with cap.n_ports.

2. When PI and cat.n_ports are inconsistent, honor cap.n_ports and
   force port_map to be ((1 << cap.n_ports) - 1).

3. There were two separate places dealing with port_map.  Unify them
   to one.

As all newer ahci chips seem to get PI correct and older ones usually
have zero PI.  Controllers with holes in PI are very unlikely to screw
up PI, so #2 makes more sense than following inconsistent PI.

Without this change, not setting ATA_FLAG_HONOR_PI when it's needed
results in weird detection failure.  This changed logic should be able
to handle all known cases correctly automatically.

Verified on ICH6 (reports 0 PI), ICH8 (with holes in port_map), ICH9,
JMB360 and JMB363.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>