- 25 5月, 2011 16 次提交
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由 Arindam Nath 提交于
Host Controller v3.00 supports programmable clock mode as an optional feature. The support for this mode is indicated by non-zero value in bits 48-55 of the Capabilities register. If supported, the actual value of Clock Multiplier is one more than the value provided in the bit fields. We only set Clock Generator Select (bit 5) and SDCLK Frequency Select (bits 8-15) of the Clock Control register in case Preset Value Enable is not set, otherwise these fields are automatically set by the Host Controller based on the UHS mode selected. Also, since the maximum and minimum clock frequency in this mode can be (Base Clock * Clock Mul) and (Base Clock * Clock Mul)/1024 respectively, f_max and f_min have been recalculated to reflect this change. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: NArindam Nath <arindam.nath@amd.com> Reviewed-by: NPhilip Rakity <prakity@marvell.com> Tested-by: NPhilip Rakity <prakity@marvell.com> Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Arindam Nath 提交于
According to the Host Controller spec v3.00, setting Preset Value Enable in the Host Control2 register lets SDCLK Frequency Select, Clock Generator Select and Driver Strength Select to be set automatically by the Host Controller based on the UHS-I mode set. This patch enables this feature. Since Preset Value Enable makes sense only for UHS-I cards, we enable this feature after successfull UHS-I initialization. We also reset Preset Value Enable next time before initialization. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: NArindam Nath <arindam.nath@amd.com> Reviewed-by: NPhilip Rakity <prakity@marvell.com> Tested-by: NPhilip Rakity <prakity@marvell.com> Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Arindam Nath 提交于
Host Controller needs tuning during initialization to operate SDR50 and SDR104 UHS-I cards. Whether SDR50 mode actually needs tuning is indicated by bit 45 of the Host Controller Capabilities register. A new command CMD19 has been defined in the Physical Layer spec v3.01 to request the card to send tuning pattern. We enable Buffer Read Ready interrupt at the very begining of tuning procedure, because that is the only interrupt generated by the Host Controller during tuning. We program the block size to 64 in the Block Size register. We make sure that DMA Enable and Multi Block Select in the Transfer Mode register are set to 0 before actually sending CMD19. The tuning block is sent by the card to the Host Controller using DAT lines, so we set Data Present Select (bit 5) in the Command register. The Host Controller is responsible for doing the verfication of tuning block sent by the card at the hardware level. After sending CMD19, we wait for Buffer Read Ready interrupt. In case we don't receive an interrupt after the specified timeout value, we fall back on fixed sampling clock by setting Execute Tuning (bit 6) and Sampling Clock Select (bit 7) of Host Control2 register to 0. Before exiting the tuning procedure, we disable Buffer Read Ready interrupt and re-enable other interrupts. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: NArindam Nath <arindam.nath@amd.com> Reviewed-by: NPhilip Rakity <prakity@marvell.com> Tested-by: NPhilip Rakity <prakity@marvell.com> Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Arindam Nath 提交于
We decide on the current limit to be set for the card based on the Capability of Host Controller to provide current at 1.8V signalling, and the maximum current limit of the card as indicated by CMD6 mode 0. We then set the current limit for the card using CMD6 mode 1. As per the Physical Layer Spec v3.01, the current limit switch is only applicable for SDR50, SDR104, and DDR50 bus speed modes. For other UHS-I modes, we set the default current limit of 200mA. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: NArindam Nath <arindam.nath@amd.com> Reviewed-by: NPhilip Rakity <prakity@marvell.com> Tested-by: NPhilip Rakity <prakity@marvell.com> Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Arindam Nath 提交于
This patch adds support for setting UHS-I bus speed mode during UHS-I initialization procedure. Since both the host and card can support more than one bus speed, we select the highest speed based on both of their capabilities. First we set the bus speed mode for the card using CMD6 mode 1, and then we program the host controller to support the required speed mode. We also set High Speed Enable in case one of the UHS-I modes is selected. We take care to reset SD clock before setting UHS mode in the Host Control2 register, and then re-enable it as per the Host Controller spec v3.00. We then set the clock frequency for the UHS-I mode selected. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: NArindam Nath <arindam.nath@amd.com> Reviewed-by: NPhilip Rakity <prakity@marvell.com> Tested-by: NPhilip Rakity <prakity@marvell.com> Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Arindam Nath 提交于
As per Host Controller spec v3.00, we reset SDCLK before setting High Speed Enable, and then set it back to avoid generating clock gliches. Before enabling SDCLK again, we make sure the clock is stable, so we use sdhci_set_clock(). Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: NArindam Nath <arindam.nath@amd.com> Reviewed-by: NPhilip Rakity <prakity@marvell.com> Tested-by: NPhilip Rakity <prakity@marvell.com> Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Arindam Nath 提交于
This patch adds support for setting driver strength during UHS-I initialization procedure. Since UHS-I cards set S18A (bit 24) in response to ACMD41, we use this as a base for UHS-I initialization. We modify the parameter list of mmc_sd_get_cid() so that we can save the ROCR from ACMD41 to check whether bit 24 is set. We decide whether the Host Controller supports A, C, or D driver type depending on the Capabilities register. Driver type B is suported by default. We then set the appropriate driver type for the card using CMD6 mode 1. As per Host Controller spec v3.00, we set driver type for the host only if Preset Value Enable in the Host Control2 register is not set. SDHCI_HOST_CONTROL has been renamed to SDHCI_HOST_CONTROL1 to conform to the spec. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: NArindam Nath <arindam.nath@amd.com> Reviewed-by: NPhilip Rakity <prakity@marvell.com> Tested-by: NPhilip Rakity <prakity@marvell.com> Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Arindam Nath 提交于
Host Controller v3.00 adds another Capabilities register. Apart from other things, this new register indicates whether the Host Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec doesn't mention about explicit support for SDR12 and SDR25 UHS-I modes, so the Host Controller v3.00 should support them by default. Also if the controller supports SDR104 mode, it will also support SDR50 mode as well. So depending on the host support, we set the corresponding MMC_CAP_* flags. One more new register. Host Control2 is added in v3.00, which is used during Signal Voltage Switch procedure described below. Since as per v3.00 spec, UHS-I supported hosts should set S18R to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also need to set XPC (bit 28) of OCR in case the host can supply >150mA. This support is indicated by the Maximum Current Capabilities register of the Host Controller. If the response of ACMD41 has both CCS and S18A set, we start the signal voltage switch procedure, which if successfull, will switch the card from 3.3V signalling to 1.8V signalling. Signal voltage switch procedure adds support for a new command CMD11 in the Physical Layer Spec v3.01. As part of this procedure, we need to set 1.8V Signalling Enable (bit 3) of Host Control2 register, which if remains set after 5ms, means the switch to 1.8V signalling is successfull. Otherwise, we clear bit 24 of OCR and retry the initialization sequence. When we remove the card, and insert the same or another card, we need to make sure that we start with 3.3V signalling voltage. So we call mmc_set_signal_voltage() with MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling voltage before we actually start initializing the card. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: NArindam Nath <arindam.nath@amd.com> Reviewed-by: NPhilip Rakity <prakity@marvell.com> Tested-by: NPhilip Rakity <prakity@marvell.com> Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Takashi Iwai 提交于
On HP laptops with JMicron 388 chip, the write-locked SD card isn't detected correctly as read-only in many cases. This is because the PRESENT_STATE register becomes unsable just after plugging, and it returns the WRITE_PROTECT bit wrongly at the first read. This patch fixes the read-only detection by adding a new sdhci quirk indicating to check the register more intensively with a relatively long delay. The patch is tested with 2.6.39-rc4 kernel. Cc: Aries Lee <arieslee@jmicron.com> Signed-off-by: NTakashi Iwai <tiwai@suse.de> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Philip Rakity 提交于
Marvell pxa controllers have private registers that may need to be modified before and after a reset is done. For example, the SD reset operation, RESET_ALL, will reset the private registers to their default state. This will cause the clock adjustment registers that may have been programmed to have incorrect values. RESET_DATA sometimes needs to be delayed before the reset is done (depending on SoC) to enable any transactions being handled by the SDIO card to be completed. Needed in pre SD 3.0 silicon to handle clock gating. Implement hooks to allow this to happen. Signed-off-by: NPhilip Rakity <prakity@marvell.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Mark Brown 提交于
Commit 373e6a (mmc: sdhci: R1B command handling + MMC_CAP_ERASE) moved the handling of SDHCI_QUIRK_TIMEOUT_USES_SDCLK from sdhci_calc_timeout() to sdhci_add_host(). This causes division by zero errors on at least the S3C SDHCI controller as the quirk implementation needs host->clock set to work but host->clock has not been set when sdhci_add_host() is called. Fix this by backing out that portion of the change, the clock may vary at runtime anyway. It does occur to me that we may want to move the quirk to where we set the clock but this seems more invasive and I'm concerned about undesirable side effects. Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com> Cc: Andrei Warkentin <andreiw@motorola.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Mikko Vinni 提交于
Some SD host controllers (noticed on an integrated JMicron SD reader on an HP Pavilion dv5-1250eo laptop) don't update the dma address register before signaling a dma interrupt due to a dma boundary. Update the register manually to the next boundary (by default 512KiB), at which the transfer stopped. As long as each transfer is at most 512KiB in size (guaranteed by a BUG_ON in sdhci_prepare_data()) and the boundary is kept at the default value, this fix is needed at most once per transfer. Smaller boundaries are taken care of by counting the transferred bytes. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=28462Signed-off-by: NMikko Vinni <mmvinni@yahoo.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Andrei Warkentin 提交于
ERASE command needs R1B response, so fix R1B-type command handling for SDHCI controller. For non-DAT commands using a busy response, the cmd->cmd_timeout_ms (in ms) field is used for timeout calculations. Based on patch by Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: NAndrei Warkentin <andreiw@motorola.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Ameya Palande 提交于
This patch fixes 21 errors and 6 warnings reported by checkpatch.pl. Signed-off-by: NAmeya Palande <2ameya@gmail.com> Reviewed-by: NWolfram Sang <w.sang@pengutronix.de> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Shawn Guo 提交于
This config option is used to decide whether tegra sdhci support should be build into the sdhci-platform module. So setting it 'm' is nonsense, since we can't build part of an module as a module. The effect for 'm' will probably be the same as for 'n'. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Venkat Rao 提交于
Enable fast bcm4329 WIFI suspend/resume on Tegra2 board. This patch allows the mach-tegra support to tell the tegra MMC host controller to NOT turn off power for the MMC controller the WIFI part lives behind. Thus bcm4329 firmware doesn't need to be reloaded. Signed-off-by: NVenkat Rao <vrao@broadcom.com> Tested-by: NGrant Grundler <grundler@chromium.org> Reviewed-by: NOlof Johansson <olof@lixom.net> Acked-by: NOlof Johansson <olof@lixom.net> Signed-off-by: NChris Ball <cjb@laptop.org>
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- 28 4月, 2011 5 次提交
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由 Chris Ball 提交于
It seems that under certain circumstances the sdhci_tasklet_finish() call can be entered with mrq set to NULL, causing the system to crash with a NULL pointer de-reference. Seen on S3C6410 system. Based on a patch by Dimitris Papastamos. Reported-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com> Cc: <stable@kernel.org> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Ben Dooks 提交于
It seems that under certain circumstances that the sdhci_tasklet_finish() call can be entered with mrq->cmd set to NULL, causing the system to crash with a NULL pointer de-reference. Unable to handle kernel NULL pointer dereference at virtual address 00000000 PC is at sdhci_tasklet_finish+0x34/0xe8 LR is at sdhci_tasklet_finish+0x24/0xe8 Seen on S3C6410 system. Signed-off-by: NBen Dooks <ben-linux@fluff.org> Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com> Cc: <stable@kernel.org> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Guennadi Liakhovetski 提交于
The aggressive clock gating for TMIO MMC patch has broken switching interface power on, using MFD or platform callbacks. Restore the ios->power_mode == MMC_POWER_UP && ios->clock == 0 case handling. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Michael Buesch 提交于
Either OMAP_MMC_STAT_CARD_ERR or OMAP_MMC_STAT_END_OF_CMD might fire if there is no host->cmd pointer. Check for a valid host->cmd pointer before calling mmc_omap_cmd_done(). Signed-off-by: NMichael Buesch <mb@bu3sch.de> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Chris Ball 提交于
If pci_ioremap_bar() fails during probe, we "goto release;" and free the host, but then we return 0 -- which tells sdhci_pci_probe() that the probe succeeded. Since we think the probe succeeded, when we unload sdhci we'll go to sdhci_pci_remove_slot() and it will try to dereference slot->host, which is now NULL because we freed it in the error path earlier. The patch simply sets ret appropriately, so that sdhci_pci_probe() will detect the failure immediately and bail out. Signed-off-by: NChris Ball <cjb@laptop.org> Cc: <stable@kernel.org>
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- 31 3月, 2011 1 次提交
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由 Lucas De Marchi 提交于
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: NLucas De Marchi <lucas.demarchi@profusion.mobi>
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- 29 3月, 2011 1 次提交
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由 Thomas Gleixner 提交于
Scripted with coccinelle. Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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- 28 3月, 2011 1 次提交
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由 Guennadi Liakhovetski 提交于
Fix build breakage on platforms, not providing readsw and writesw functions, e.g., on x86(_64). Reported-by: NStephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: NChris Ball <cjb@laptop.org>
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- 27 3月, 2011 1 次提交
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由 Simon Horman 提交于
Also add TMIO_BBS. This allows these defines to also be used by zboot. Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: NSimon Horman <horms@verge.net.au> Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: NPaul Mundt <lethal@linux-sh.org> Signed-off-by: NChris Ball <cjb@laptop.org>
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- 25 3月, 2011 15 次提交
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由 Guennadi Liakhovetski 提交于
Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: NPaul Mundt <lethal@linux-sh.org> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Guennadi Liakhovetski 提交于
The power-mode sequence on MMC is MMC_POWER_OFF -> MMC_POWER_UP -> MMC_POWER_ON and not MMC_POWER_ON -> MMC_POWER_UP, as the driver currently is implying. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: NPaul Mundt <lethal@linux-sh.org> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Guennadi Liakhovetski 提交于
SDIO IRQs got unmasked on sh-mobile while writing to the CTL_CLK_AND_WAIT_CTL register, because that register at address 0x138 is not implemented on those SoCs and writes to it overwrite the register at address 0x38: CTL_SDIO_IRQ_MASK. Previous patches eliminated access to register above 0xff on sh-mobile, so that this work-around isn't needed anymore. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: NPaul Mundt <lethal@linux-sh.org> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Guennadi Liakhovetski 提交于
Not all tmio implementations have registers above oxff. Accessing them on thise platforms is dangerous. In some cases it leads to address wrapping to addresses below 0x100, which corrupts random unrelated registers. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: NPaul Mundt <lethal@linux-sh.org> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Guennadi Liakhovetski 提交于
On sh-mobile platforms the SDHI driver was using the tmio_mmc SD/SDIO MFD cell driver. Now that the tmio_mmc driver has been split into a core and a separate MFD glue, we can support SDHI natively without the need to emulate an MFD controller. This also allows to support systems with an on-SoC SDHI controller and a separate MFD with a TMIO core. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: NPaul Mundt <lethal@linux-sh.org> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Guennadi Liakhovetski 提交于
TMIO MMC chips contain an SD / SDIO IP core from Panasonic, similar to the one, used in MN5774 and other MN57xx controllers. These IP cores are included in many multifunction devices, in sh-mobile chips from Renesas, in the latter case they can also use DMA. Some sh-mobile implementations also have some other specialities, that MFD-based solutions don't have. This makes supporting all these features in a monolithic driver inconveniet and error-prone. This patch splits the driver into 3 parts: the core, the MFD glue and the DMA support. In case of a modular build, two modules will be built: mmc_tmio_core and mmc_tmio. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: NPaul Mundt <lethal@linux-sh.org> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Guennadi Liakhovetski 提交于
This patch allows transferring of some requests in PIO and some in DMA mode and defaults to using DMA only for transfers longer than 8 bytes. This is especially useful with SDIO, which can have lots of 2- and 4-byte transfers, creating unnecessary high overhead, when executed in DMA. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: NPaul Mundt <lethal@linux-sh.org> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Guennadi Liakhovetski 提交于
On some SDHI tmio implementations the order of DMA and command completion interrupts swaps, which leads to malfunction. This patch postpones DMA activation until the MMC command completion IRQ time. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: NPaul Mundt <lethal@linux-sh.org> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Richard Zhu 提交于
Fix the NO INT in the Multi-BLK IO in SD/MMC, and Multi-BLK read in SDIO on imx53. The CMDTYPE of the CMD register (offset 0xE) should be set to "11" when the STOP CMD12 is issued on imx53 to abort one open ended multi-blk IO. Otherwise the TC INT wouldn't be generated. In exact block transfer, the controller doesn't complete the operations automatically as required at the end of the transfer and remains on hold if the abort command is not sent on imx53. As a result, the TC flag is not asserted and SW receives timeout exception. Set bit1 of Vendor Spec register to fix it. Signed-off-by: NRichard Zhu <Hong-Xing.Zhu@freescale.com> Signed-off-by: NRichard Zhao <richard.zhao@freescale.com> Reviewed-by: NWolfram Sang <w.sang@pengutronix.de> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Richard Zhu 提交于
Add one flag to indicate the GPIO CD/WP is enabled or not on imx platforms, and reuse the writel/readl as the general APIs for imx SOCs. Signed-off-by: NRichard Zhu <Hong-Xing.Zhu@freescale.com> Reviewed-by: NWolfram Sang <w.sang@pengutronix.de> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Richard Zhu 提交于
Add the abort CMDTYPE bits definition of command register (offset 0xE) Signed-off-by: NRichard Zhu <Hong-Xing.Zhu@freescale.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Richard Zhu 提交于
sdhci-esdhc-imx does not need SDHCI_QUIRK_NO_CARD_NO_RESET. Make it OF-specific. Signed-off-by: NRichard Zhu <Hong-Xing.Zhu@freescale.com> Tested-by: NWolfram Sang <w.sang@pengutronix.de> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 David Miller 提交于
Since these are the headers that provide irq_of_parse_and_map() and NO_IRQ. Signed-off-by: NDavid S. Miller <davem@davemloft.net> Acked-by: NGrant Likely <grant.likely@secretlab.ca> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Pawel Moll 提交于
New IO FPGA implementation for Versatile Express boards contain MMCI (PL180) cell with FIFO extended to 128 words (512 bytes). Matt Waddel reports that this patch improves MMC performance on his vexpress system, and also fixes "mmcblk0: error -5 transferring data" errors. Signed-off-by: NPawel Moll <pawel.moll@arm.com> Tested-by: NMatt Waddel <matt.waddel@linaro.org> Signed-off-by: NChris Ball <cjb@laptop.org>
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由 Jaehoon Chung 提交于
This patch uses the fixed burst bit when using an internal DMA controller. I found increased performance with IDMAC when this bit is set. Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Signed-off-by: NChris Ball <cjb@laptop.org>
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