This patch adds required structures for powerdomain initialization on
the ti816x. It is impossible to use omap3430 structures in order to
initialize powerdomains on ti816x, because there are big differences
between PRCM module base address offsets on these CPUs.
Signed-off-by: NAida Mynzhasova <aida.mynzhasova@skitlab.ru>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Currently omap3xxx_check_revision() detects ES1.0 and ES1.1 only,
this patch extends it by adding ES2.0 and ES2.1 versions support.
Signed-off-by: NAida Mynzhasova <aida.mynzhasova@skitlab.ru>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Describe minimal DT boot machine details for AM43x based SoC's. AM43x
SoC's are ARM Cortex-A9 based with one core. AM43x is similar to
AM335x w.r.t L4 PER/WKUP memory map. AM43x has a sync timer, here that
is being used as clocksource, while 1ms dmtimer as clockevent.
Signed-off-by: NAnkur Kishore <a-kishore@ti.com>
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This definition corresponds to the L3_OCMC0,
as in case of AM33XX.
Signed-off-by: NSanjeev Premi <premi@ti.com>
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
[tony@atomide.com: updated to remove default y]
Signed-off-by: NTony Lindgren <tony@atomide.com>

Detect whether GP or HS, similar to the AM335x way.
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Minimal early init - PRCM initialization not yet taken care.

Control module is similar (base address, feature register etc.) as
that of AM335x, while PRCM base address is different. Instead of
adding a new header file for AM43x, PRCM base address is added in
AM335x header file as it is similar to it to a large extent.
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
[tony@atomide.com: updated to drop am33xx_check_features()]
Signed-off-by: NTony Lindgren <tony@atomide.com>

AM43x L4 WKUP/PER mappings are similar to AM335x, reuse.
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Detect 437x SoC revision.
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

soc_is support for AM43x family of SoC's. Only variant now is AM437x,
it is made as a subclass of AM43x.
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Build pieces that could be reused for AM43x - GIC related, secure
related and common PRCM.
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Kconfig for AM43x (Cortex A9) family of SoC's.
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Separate out OMAP4 restart and have it similar to other platforms, in
a different file. Main motive is to reuse omap4-common on platforms
other than OMAP4, like AM43x, even if OMAP4 is deselected (otherwise
would have caused build breakage).
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

EHRPWM module requires explicit clock gating of TBCLK from control
module. Hence add TBCLK clock node in clock tree for EHRPWM modules.
Signed-off-by: NPhilip Avinash <avinashphilip@ti.com>
[bigeasy: remove CK_AM33XX]
Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

We don't need multiple aliases for the OMAP USB host clocks and neither
the dummy clocks so remove them.

CC: Paul Walmsley <paul@pwsan.com>
CC: Rajendra Nayak <rnayak@ti.com>
CC: Benoit Cousson <b-cousson@ti.com>
CC: Mike Turquette <mturquette@linaro.com>
Signed-off-by: NRoger Quadros <rogerq@ti.com>
[paul@pwsan.com: updated against v3.10-rc4]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

GFX has a reset status register (PRM_GFX.RM_GFX_RSTST),
so update the GFX hwmod data with .rstst_off and .st_shift
information.
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

If the early MMU mapping of the UART happens to get booted out of the
TLB between the start of paging_init() and when we finally re-add the
UART at the very end of s3c_init_cpu(), we'll get a hang at bootup if
we've got early_printk enabled.  Avoid this hang by calling
debug_ll_io_init() early.

Without this patch, you can reliably reproduce a hang when early
printk is enabled by adding flush_tlb_all() at the start of
exynos_init_io().  After this patch the hang goes away.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Printing low-level debug messages make an assumption that the specified
UART port has been preconfigured by the bootloader. Incorrectly
specified UART port results in system getting stalled while printing the
message "Uncompressing Linux... done, booting the kernel"
This UART port number is specified through S3C_LOWLEVEL_UART_PORT. Since
the UART port might different for different board, it is not possible to
specify it correctly for every board that use a common defconfig file.

Calling this print subroutine only when DEBUG_LL fixes the problem. By
disabling DEBUG_LL in default config file, we would be able to boot
multiple boards with different default UART ports.

With this current approach, we miss the print "Uncompressing Linux...
done, booting the kernel." when DEBUG_LL is not defined.
Signed-off-by: NTushar Behera <tushar.behera@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Since the introduction of preemptible mmu_gather TLB fast mode has been
broken. TLB fast mode relies on there being absolutely no concurrency;
it frees pages first and invalidates TLBs later.

However now we can get concurrency and stuff goes *bang*.

This patch removes all tlb_fast_mode() code; it was found the better
option vs trying to patch the hole by entangling tlb invalidation with
the scheduler.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Tony Luck <tony.luck@intel.com>
Reported-by: NMax Filippov <jcmvbkbc@gmail.com>
Signed-off-by: NPeter Zijlstra <peterz@infradead.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Update the CMT clockevent rating from 125 to 80.

This resolves a boot-failure regression for kzm9g-reference in v3.10-rc1
introduced by f7db706b ("ARM: 7674/1: smp:
Avoid dummy clockevent being preferred over real").

The patch noted above reduces the rating of dummy clockevent from 400 to 100.
This patch reduces the rating of CMT so that it is once again less than that
of the dummy clockevent.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The KVM/ARM MMU code doesn't take care of invalidating TLBs before
freeing a {pte,pmd} table. This could cause problems if the page
is reallocated and then speculated into by another CPU.
Reported-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NChristoffer Dall <cdall@cs.columbia.edu>

Some ARM KVM VCPU ioctls require the vCPU to be properly initialized
with the KVM_ARM_VCPU_INIT ioctl before being used with further
requests. KVM_RUN checks whether this initialization has been
done, but other ioctls do not.
Namely KVM_GET_REG_LIST will dereference an array with index -1
without initialization and thus leads to a kernel oops.
Fix this by adding checks before executing the ioctl handlers.

 [ Removed superflous comment from static function - Christoffer ]

Changes from v1:
 * moved check into a static function with a meaningful name
Signed-off-by: NAndre Przywara <andre.przywara@linaro.org>
Signed-off-by: NChristoffer Dall <cdall@cs.columbia.edu>

The AXI clock mux should be as below:

00: periph;
01: pll2_pfd2_396m;
10: periph;
11: pll3_pfd1_540m;
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Stephen Warren reported the recent commit 78506f22 (add support for
extended FIFO-size of PL011-r1p5) breaks the serial port on the
BCM2835 ARM SoC.

A UART compatible with the ARM PL011-r1p5 should have 32-deep FIFOs.
The BCM2835 UART just looks like an ARM PL011-r1p5, but has 16-deep
FIFOs just like PL011-r1p4 or earlier revisions. As a workaround for
this compatibility issue, this patch overrides the HW UART periphid
register values with the actually compatible UART periphid 0x00241011
(r1p3 or r1p4).
Reported-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NJongsung Kim <neidhard.kim@lge.com>
Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This turns on a number of configs that are useful on the Chromebook, but also
good to have on in general:

* USB host and MMC drivers(!)
* I2C GPIO arbitration driver
* CYAPA trackpad driver
* simplefb
* CROS EC and keyboard drivers
* S5M8767 driver
* MAX77686 drivers
* MAX8997 driver
* DEVTMPFS + mount
* DM_CRYPT (as module)
* CRYPTOLOOP
* HIGHMEM
* PRINTK timestamps

This also turns off DEBUG_LL, and switches the hardcoded Samsung lowlevel
uart to uart 3 (which is only used to show the "uncompressing kernel"
message at boot, it seems).
Signed-off-by: NOlof Johansson <olof@lixom.net>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NTushar Behera <tushar.behera@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>

When adding CPU to the SMP group and enabling the coherency on this
CPU we must protect the register access.
The previous implementation claims to be atomic but doesn't provide
any protection against parallel access to the coherency fabric control
and configuration registers.

This patch fixes this by using the ldrex and strex mechanism.
This method should be used in all accesses to those registers.

[gregory.clement@free-electrons.com: fixed the commit's topic]
Signed-off-by: NNadav Haklai <nadavh@marvell.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

When creating the DT based boards-ts219.c the none DT ts219-setup.c
was used as a template. This includes a lateinit() call to initialize
the PCIe bus. The code makes use of machine_is_ts219() which is never
true on DT, so a FIXME was added and the code left as is. This was
unproblematic until b73690c8: "ARM: Kirkwood: Support basic
hotplug for PCI-E" which changes the way the PCIe bus is
initialized. The non-DT ts219-setup.c now crashes during boot.  The
lateinit() call in the DT boards-ts219.c is being called,
machine_is_ts219() is true and so the PCIe is initialized a second
time.

This patch removes the useless, and now clearly dangerous, code from
boards-ts219.c, making ts219-setup.c work again.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Cc: <stable@vger.kernel.org> # v3.9.x
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

On DT-enabled systems pinctrl-exynos driver is responsible for handling
of wake-up EINT interrupts. This patch adjusts wake-up mask
configuration code to take wake-up mask value from pinctrl-exynos driver
on DT-enabled systems.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch fixes a bug introduced in the v3.10 merge window.

The AB8500 External Regulator driver has recently landed upstream,
which registers each of the 3 external regulators located on the
AB8500. If these regulators are marked as 'always on', there is a
potential for power-loss. If they're not and are seemingly unused
the Regulator subsystem will attempt to disable them to save power.
This causes an issue for AUX1, AUX2 and AUX3 as they obtain their
power from EXT3. So we're specifying that here to prevent EXT3 from
being powered down.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Multiplatform calls all enabled platforms' initcalls. In the
ux500_idle_init() initcall we call into the DBx500-PRCMU which in turn
executes some ux500 specific register reads/writes. When running on
some !ux500 platforms this ends up causing a kernel Oops. This patch
ensures the PRCMU call is only invoked when running on ux500 based
platforms.
Reported-by: NRob Herring <rob.herring@calxeda.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Since commit 1977e6d8 (drm/exynos: change the method for getting the
interrupt) the Exynos DRM FIMD driver requires IRQ resources to be
named. This patch fixes probe failure in non-DT cases by adding
appropriate resource names to fimd0 platform device.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch fixes software reset logic. Software reset applies only to
powered-on domains in SOC because software reset to all domains causes
reboot failure.
Signed-off-by: NJungseok Lee <jays.lee@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch extends exynos_init_time() function to handle Exynos4210
rev0 SoC, which differs in availability of system timers and needs
different clocksource initialization.

This makes it possible to use exynos_init_time() function as init_time
callback for all Exynos-based boards, including Universal_C210, which
originally had to use samsung_timer_init().
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The PA24 pin is wrongly assigned to peripheral B.
In the current config there is 2 ETX3 pins (PA11 and PA24) and
no ETXER pin (PA22).
Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Cc: stable <stable@vger.kernel.org> # 3.8+

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The CSPI controller has only one clock, but the driver spi-imx.c needs
clock "per" to calculate bitrate divisor.
Signed-off-by: NJonas Andersson <jonas@microbit.se>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

As pll5_video_div has been introduced to represent the clock
generated from post-divider for video.
Instead of pll5_video, pll5_video_div should be proper root clock
for ldb_di_sel.
Signed-off-by: NJiada Wang <jiada_wang@mentor.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Commit d3f79584 ("ARM: cleanup undefined instruction entry code")
improved the register scheduling when handling undefined instructions.
A side effect of this is that r5 is now used as a temporary, whilst the
VFP probing code relies on r5 containing a non-zero value when VFP is
not supported.

This patch fixes the VFP detection code so that we don't rely on the
contents of r5. Without this patch, Linux dies loudly on CPUs without
VFP support.
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

If one reads /proc/$PID/smaps, the mmap_sem belonging to the
address space of the task being examined is locked for reading.
All the pages of the vmas belonging to the task's address space
are then walked with this lock held.

If a gate_vma is present in the architecture, it too is examined
by the fs/proc/task_mmu.c code. As gate_vma doesn't belong to the
address space of the task though, its pages are not walked.

A recent cleanup (commit f6604efe) of the gate_vma initialisation
code set the vm_mm value to &init_mm. Unfortunately a non-NULL
vm_mm value in the gate_vma will cause the task_mmu code to attempt
to walk the pages of the gate_vma (with no mmap-sem lock held). If
one enables Transparent Huge Page support and vm debugging, this
will then cause OOPses as pmd_trans_huge_lock is called without
mmap_sem being locked.

This patch removes the .vm_mm value from gate_vma, restoring the
original behaviour of the task_mmu code.
Signed-off-by: NSteve Capper <steve.capper@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Make the SHA1 asm code ABI conformant by making sure all stack
accesses occur above the stack pointer.

Origin:
http://git.openssl.org/gitweb/?p=openssl.git;a=commit;h=1a9d60d2Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: NNicolas Pitre <nico@linaro.org>
Cc: stable@vger.kernel.org
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>