- 18 3月, 2015 13 次提交
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由 Matt Roper 提交于
With the switch to atomic plumbing for planes, some of our commit-time work (e.g., watermarks) is done after the new atomic state is swapped into the relevant DRM object, but before the DRM core has a chance to update its legacy state values. Switch intel_crtc_active() to look at the state objects rather than legacy fields to ensure we operate on the proper values. Note that we're continuing to use intel_crtc->active here for the time being since crtc->state isn't really hooked up yet. Once CRTC states are wired up properly, we'll want to switch this over to use crtc->state->active instead. v2: Switch back to intel_crtc->active for now; when Ander's work on CRTC states is ready, we can flip this over to use crtc->state->active instead. (Ville) Cc: Ander Conselvan De Oliveira <conselvan2@gmail.com> Suggested-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NMatt Roper <matthew.d.roper@intel.com> Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
The specs seem to be full of misinformation wrt. the Punit register 0x36. Some versions still show the old VLV bit layout, some the new layout, and all of them seem to tell us nonsense about the cdclk value encoding. Testing on actual hardware has shown that we simply need to program the desired CCK divider into the Punit register using the new layout of the bits. Doing that, the status bit change to indicate the same value, and the CCK 0x6b register also changes accordingly to indicate that CCK is now using the new divider. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NVijay Purushothaman <vijay.a.purushothaman@linux.intel.com> Reviewed-by: NYogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
Supposedly CHV can sustain a pixel clock of up to 95% of cdclk, as opposed to the 90% limit that was used old older platforms. Update the cdclk selection code to allow for this. This will allow eg. HDMI 4k modes with their 297MHz pixel clock while still respecting the 320 MHz cdclk limit on CHV. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NVijay Purushothaman <vijay.a.purushothaman@linux.intel.com> Reviewed-by: NYogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Jesse Barnes 提交于
So try to enumerate eDP unconditionally in those cases. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> [danvet: Add wa tag Damien dug out.] Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 John Harrison 提交于
Apparently, this has never worked reliably and is currently disabled. Also, the gains are not particularly impressive. Thus rather than try to keep unused code from decaying and having to update it for other driver changes, it was decided to simply remove it. For: VIZ-5115 Signed-off-by: NJohn Harrison <John.C.Harrison@Intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Matt Roper 提交于
We need to disable all sprite planes when disabling the CRTC. We had been using the top-level atomic 'disable' entrypoint to accomplish this, which was wrong. Not only can this lead to various locking issues, it also modifies the actual plane state, making it impossible to restore the plane properly later. For example, a DPMS off followed by a DPMS on will result in any sprite planes in use not being restored properly. The proper solution here is to call directly into our 'commit plane' hook with a copy of the plane's current state that has 'visible' set to false. Committing this dummy state will turn off the plane, but will not touch the actual plane->state pointer, allowing us to properly restore the plane state later. Signed-off-by: NMatt Roper <matthew.d.roper@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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When logging that full mode switch is necessary, log which connector, encoder or crtc has caused it, so it is easier to figure out what is goind on by just looking at the log. Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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We have similar macros for crtcs and encoders, and the pattern happens often enough to justify the macro. Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
The current minimum vco frequency leaves us with a gap in our supported frequencies at 233-243 MHz. Your typical 2560x1440@60 display wants a pixel clock of 241.5 MHz, which is just withing that gap. Reduce the allowed vco min frequency to 4.8GHz to reduce the gap to 233-240 MHz, and thus allow such displays to work. 4.8 GHz is actually the documented (at least in some docs) limit of the PLL, and we just picked 4.86 GHz originally because that was the lowest value produced by the PLL spreadsheet, which obviously didn't consider 2560x1440 displays. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NVijay Purushothaman <vijay.a.purushothaman@linux.intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Daniel Vetter 提交于
This reverts commit 3f678c96. We've been a bit too optimistic with this one here :( The trouble is that internally we're still using these plane update/disable hooks. Which was totally ok pre-atomic since the drm core did all the book-keeping updating and these just mostly updated hw state. But with atomic there's lots more going on, and it causes heaps of trouble with the load detect code. This one specifically cause a deadlock since both the load detect code and the nested plane atomic helper functions tried to grab the same locks. It only blows up because of the evil tricks though we play with the implicit ww acquire context. Applying this revert unearths the NULL deref on already freed framebuffer objects reported as a regression in 4.0 by various people. Fixing this will be fairly invasive, hence revert even for the 4.1-next queue. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Paul Bolle <pebolle@tiscali.nl> Acked-by: NMatt Roper <matthew.d.roper@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com>
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由 Damien Lespiau 提交于
Implicit usage of local variables in macros isn't exactly the greatest thing in the world, especially when that variable is the drm device and we want to move towards a broader use of the i915 device structure. Let's make for_each_sprite() take dev_priv as its first argument then. Suggested-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Reviewed-by: Chris Wilson <chris-wilson.co.uk> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Damien Lespiau 提交于
Implicit usage of local variables in macros isn't exactly the greatest thing in the world, especially when that variable is the drm device and we want to move towards a broader use of the i915 device structure. Let's make for_each_plane() take dev_priv as its first argument then. Suggested-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Reviewed-by: Chris Wilson <chris-wilson.co.uk> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Matt Roper 提交于
The cursor size fields in intel_crtc just duplicate the data from cursor->state.crtc_{w,h} so we don't need them any more. Worse, their use in the watermark code actually introduces a subtle bug since they don't get updated to mirror the state values until the plane commit stage, which is *after* we've already used them to calculate new watermark values. This happens because we had to move watermark updates slightly earlier (outside vblank evasion) in commit commit 32b7eeec Author: Matt Roper <matthew.d.roper@intel.com> Date: Wed Dec 24 07:59:06 2014 -0800 drm/i915: Refactor work that can sleep out of commit (v7) Dropping the intel_crtc fields and just using the state values (which are properly updated by the time watermark updates happen) should solve the problem. Aside from the actual removal of the struct fields (which are formatted in a way that I couldn't figure out how to match in Coccinelle), the rest of this patch was generated via the following semantic patch: // Drop assignment @@ struct intel_crtc *C; struct drm_plane_state S; @@ ( - C->cursor_width = S.crtc_w; | - C->cursor_height = S.crtc_h; ) // Replace usage @@ struct intel_crtc *C; expression E; @@ ( - C->cursor_width + C->base.cursor->state->crtc_w | - C->cursor_height + C->base.cursor->state->crtc_h | - to_intel_crtc(E)->cursor_width + E->cursor->state->crtc_w | - to_intel_crtc(E)->cursor_height + E->cursor->state->crtc_h ) v2: Rebase Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Joe Konno <joe.konno@linux.intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89346Signed-off-by: NMatt Roper <matthew.d.roper@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 10 3月, 2015 1 次提交
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由 Ville Syrjälä 提交于
commit a8c6ecb3 Merge: 8dd0eb35 9eccca08 Author: Dave Airlie <airlied@redhat.com> Date: Mon Mar 9 19:58:30 2015 +1000 Merge tag 'v4.0-rc3' into drm-next managed to pick the wrong code to resolve the conflict and left us with a mutex_lock(struct_mutex) without the mutex_unlock(struct_mutex) leading to a deadlock. Fix the problem by recovering the correct code which doesn't need the lock. Cc: Dave Airlie <airlied@redhat.com> Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 05 3月, 2015 1 次提交
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由 Tvrtko Ursulin 提交于
Use cases like rotation require these hooks to have some context so they know how to prepare and cleanup the frame buffer correctly. For i915 specifically, object backing pages need to be mapped differently for different rotation modes and the driver needs to know which mapping to instantiate and which to tear down when transitioning between them. v2: Made passed in states const. (Daniel Vetter) [airlied: add mdp5 and atmel fixups] Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: dri-devel@lists.freedesktop.org Reviewed-by: NRob Clark <robdclark@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 04 3月, 2015 1 次提交
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由 Daniel Vetter 提交于
This is a tricky story of the new atomic state handling and the legacy code fighting over each another. The bug at hand is an underrun of the framebuffer reference with subsequent hilarity caused by the load detect code. Which is peculiar since the the exact same code works fine as the implementation of the legacy setcrtc ioctl. Let's look at the ingredients: - Currently our code is a crazy mix of legacy modeset interfaces to set the parameters and half-baked atomic state tracking underneath. While this transition is going we're using the transitional plane helpers to update the atomic side (drm_plane_helper_disable/update and friends), i.e. plane->state->fb. Since the state structure owns the fb those functions take care of that themselves. The legacy state (specifically crtc->primary->fb) is still managed by the old code (and mostly by the drm core), with the fb reference counting done by callers (core drm for the ioctl or the i915 load detect code). The relevant commit is commit ea2c67bb Author: Matt Roper <matthew.d.roper@intel.com> Date: Tue Dec 23 10:41:52 2014 -0800 drm/i915: Move to atomic plane helpers (v9) - drm_plane_helper_disable has special code to handle multiple calls in a row - it checks plane->crtc == NULL and bails out. This is to match the proper atomic implementation which needs the crtc to get at the implied locking context atomic updates always need. See commit acf24a39 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Tue Jul 29 15:33:05 2014 +0200 drm/plane-helper: transitional atomic plane helpers - The universal plane code split out the implicit primary plane from the CRTC into it's own full-blown drm_plane object. As part of that the setcrtc ioctl (which updated both the crtc mode and primary plane) learned to set crtc->primary->crtc on modeset to make sure the plane->crtc assignments statate up to date in commit e13161af Author: Matt Roper <matthew.d.roper@intel.com> Date: Tue Apr 1 15:22:38 2014 -0700 drm: Add drm_crtc_init_with_planes() (v2) Unfortunately we've forgotten to update the load detect code. Which wasn't a problem since the load detect modeset is temporary and always undone before we drop the locks. - Finally there is a organically grown history (i.e. don't ask) around who sets the legacy plane->fb for the various driver entry points. Originally updating that was the drivers duty, but for almost all places we've moved that (plus updating the refcounts) into the core. Again the exception is the load detect code. Taking all together the following happens: - The load detect code doesn't set crtc->primary->crtc. This is only really an issue on crtcs never before used or when userspace explicitly disabled the primary plane. - The plane helper glue code short-circuits because of that and leaves a non-NULL fb behind in plane->state->fb and plane->fb. The state fb isn't a real problem (it's properly refcounted on its own), it's just the canary. - Load detect code drops the reference for that fb, but doesn't set plane->fb = NULL. This is ok since it's still living in that old world where drivers had to clear the pointer but the core/callers handled the refcounting. - On the next modeset the drm core notices plane->fb and takes care of refcounting it properly by doing another unref. This drops the refcount to zero, leaving state->plane now pointing at freed memory. - intel_plane_duplicate_state still assume it owns a reference to that very state->fb and bad things start to happen. Fix this all by applying the same duct-tape as for the legacy setcrtc ioctl code and set crtc->primary->crtc properly. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Paul Bolle <pebolle@tiscali.nl> Cc: Rob Clark <robdclark@gmail.com> Cc: Paulo Zanoni <przanoni@gmail.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Matt Roper <matthew.d.roper@intel.com> Reported-and-tested-by: NLinus Torvalds <torvalds@linux-foundation.org> Reported-by: NPaul Bolle <pebolle@tiscali.nl> Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 28 2月, 2015 7 次提交
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由 Tvrtko Ursulin 提交于
By this patch all underlying bits have been implemented and this patch actually enables the feature. v2: Validate passed in fb modifiers to reject garbage. (Daniel Vetter) v3: Rearrange validation checks per code review comments. (Daniel Vetter) Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> (v1) Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Tvrtko Ursulin 提交于
Display watermarks need different programming for different tiling modes. Set the relevant flag so this happens during the plane commit and add relevant data into a structure made available to the watermark computation code. v2: Pass in tiling info to sprite plane updates as well. v3: Rebased for plane handling changes. v4: Handle fb == NULL when plane is disabled. v5: Refactored for addfb2 interface. v6: Refactored for fb modifier changes. v7: Updated for atomic commit by only updating watermarks when tiling changes. v8: BSpec watermark calculation updates. v9: Restrict scope of y_tile_minimum variable. (Damien Lespiau) v10: Get fb from plane state otherwise we are working on old state. Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Acked-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Acked-by: NMatt Roper <matthew.d.roper@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> (v9) Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Damien Lespiau 提交于
v2: Rebased for addfb2 interface and consolidated a bit. (Tvrtko Ursulin) v3: Rebased for fb modifier changes. (Tvrtko Ursulin) v4: Use intel_fb_stride_alignment instead of open coding. (Damien Lespiau) Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Damien Lespiau 提交于
1Mb! v2: Rebased for addfb2 interface. (Tvrtko Ursulin) v3: Rebased for fb modifier changes. (Tvrtko Ursulin) Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Damien Lespiau 提交于
We now need the bpp of the fb as Yf tiling has different tile widths depending on it. v2: Rebased for the new addfb2 interface. (Tvrtko Ursulin) v3: Rebased for fb modifier changes. (Tvrtko Ursulin) v4: Added missing case and 128-bit pixel warning. (Damien Lespiau) Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> (v3) Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Damien Lespiau 提交于
Skylake is able to scannout those tiling formats. We need to allow them in the ADDFB ioctl and tell the harware about it. v2: Rebased for addfb2 interface. (Tvrtko Ursulin) v3: Rebased for fb modifier changes. (Tvrtko Ursulin) v4: Don't allow Y tiled fbs just yet. (Tvrtko Ursulin) v5: Check for stride alignment and max pitch. (Tvrtko Ursulin) v6: Simplify maximum pitch check. (Ville Syrjälä) v7: Drop the gen9 check since requirements are no different. (Ville Syrjälä) v8: Gen2 has different X tiling stride. (Ville Syrjälä) Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> (v7) Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Daniel Vetter 提交于
Mostly just checks in i915-private modeset ioctls. Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com> Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 26 2月, 2015 3 次提交
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The code in function intel_crtc_compute_config() that evens pipe_src_w if necessary would look at the current config instead of the staged one when deciding if there is an LVDS encoder in use. This could potentially lead to the value not being updated, if during the modeset a crtc wasn't driving an LVDS encoder. Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Matt Roper 提交于
As we transition to full atomic modesetting, we want to be able to pass intel_crtc_state around in various places that we pass intel_crtc directly today. Ensure that the ->crtc backpointer is properly initialized in case we need to get back to the associated CRTC. Signed-off-by: NMatt Roper <matthew.d.roper@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Matt Roper 提交于
As vendors transition their drivers from legacy to atomic there's some duplication of data between drm_crtc and drm_crtc_state (since unconverted drivers likely won't have a state structure). i915 is partially converted and does have a crtc->state structure, but still uses direct crtc fields internally in many places, which causes the two sets of data to get out of sync. As of commit commit 31c946e8 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Sun Feb 22 12:24:17 2015 +0100 drm: If available use atomic state in getcrtc ioctl This way drivers fully converted to atomic don't need to update these legacy state variables in their modeset code any more. Reviewed-by: NRob Clark <robdclark@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com> the DRM core starts assuming that the presence of a ->state structure implies that it should make use of the values stored there which, on i915, leads to the core code using stale values for CRTC 'enabled' status. Let's switch over to using the state value of 'enable' internally rather than using the drm_crtc field. This ensures that our driver internals are working from the same data that the DRM core is, avoiding mismatches. This patch was generated with Coccinelle using the following semantic patch: <smpl> @@ struct drm_crtc C; struct drm_crtc *CP; @@ ( - C.enabled + C.state->enable | - CP->enabled + CP->state->enable ) // For assignments, we still update the legacy value as well as the state value // so add an extra assignment statement for that. @@ struct drm_crtc C; struct drm_crtc *CP; expression E; @@ ( C.state->enable = E; + C.enabled = E; | CP->state->enable = E; + CP->enabled = E; ) </smpl> The crtc->mode and crtc->hwmode fields should probably be transitioned over as well eventually, but we seem to do an okay job of keeping those up-to-date already so I want to minimize the changes that will clash with Ander's in-progress atomic work. v2: Don't remove the assignments to the legacy value when we assign to the state value. A second cocci stanza takes care of adding the legacy assignment back where appropriate. (Daniel) Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: NMatt Roper <matthew.d.roper@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 25 2月, 2015 1 次提交
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由 Rodrigo Vivi 提交于
This return 0 without setting atomic bits on fb == crtc->cursor->fb where causing frontbuffer false positives. According to Daniel: The original regression seems to have been introduced in the original check/commit split: commit 757f9a3e Author: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Date: Wed Sep 24 14:20:24 2014 -0300 drm/i915: move check of intel_crtc_cursor_set_obj() out Which already cause other trouble, resulting in the check getting moved in commit e391ea88 Author: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Date: Wed Sep 24 14:20:25 2014 -0300 drm/i915: Fix not checking cursor and object sizes The frontbuffer tracking itself only was broken when we shifted it into the check/commit logic with: commit 32b7eeec Author: Matt Roper <matthew.d.roper@intel.com> Date: Wed Dec 24 07:59:06 2014 -0800 drm/i915: Refactor work that can sleep out of commit (v7) v2: When putting more debug prints I notice the solution was simpler than I thought. AMS design is solid, just this return was wrong. Sorry for the noise. v3: Remove the entire chunck that would probably be removed by gcc anyway. (by Daniel) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: NMatt Roper <matthew.d.roper@intel.com> Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NJani Nikula <jani.nikula@intel.com>
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- 24 2月, 2015 4 次提交
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由 Daniel Vetter 提交于
Some bios really like to joke and start the planes at an offset ... hooray! Align start and end to fix this. v2: Fixup calculation of size, spotted by Chris Wilson. v3: Fix serious fumble I've just spotted. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86883 Cc: stable@vger.kernel.org Cc: Johannes W <jargon@molb.org> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula@linux.intel.com> Reported-and-tested-by: NJohannes W <jargon@molb.org> Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com> [Jani: split WARN_ONs, rebase on v4.0-rc1] Signed-off-by: NJani Nikula <jani.nikula@intel.com>
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由 Durgadoss R 提交于
This patch enables eDP DRRS for CHV by adding the required IS_CHERRYVIEW() checks. CHV uses the same register bit as VLV. [Vandana]: Since CHV has 2 sets of M_N registers, it will follow the same code path as gen < 8. Added CHV check in dp_set_m_n() [Ram]: Rebased on top of previous patch modifications Signed-off-by: NDurgadoss R <durgadoss.r@intel.com> Signed-off-by: NVandana Kannan <vandana.kannan@intel.com> Signed-off-by: NRamalingam C <ramalingam.c@intel.com> Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ramalingam C 提交于
Till Gen 7 we have two sets of M_N registers, but Gen 8 onwards we have only one M_N register set. To support DRRS on both scenarios a input parameter to intel_dp_set_m_n is added. In case of DRRS, When platform provides two set of M_N registers for dp, we can program them with two different dividers and switch between them. But when only one such register set is provided, we have to program the required divider M_N value on that registers itself. Two enum members M1_N1 and M2_N2 are defined to represent the above scenarios. M1_N1 : Program dp_m_n on M1_N1 registers dp_m2_n2 on M2_N2 registers (If supported) M2_N2 : Program dp_m2_n2 on M1_N1 registers M2_N2 registers are not supported Signed-off-by: NRamalingam C <ramalingam.c@intel.com> Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Vijay Purushothaman 提交于
As per the recommendation from PHY team, limit the max vco supported in CHV to 6.48 GHz Signed-off-by: NVijay Purushothaman <vijay.a.purushothaman@linux.intel.com> Acked-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 23 2月, 2015 4 次提交
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由 Jani Nikula 提交于
Add quirk for Dell Chromebook 11 backlight. Reported-and-tested-by: NOwen Garland <garland.owen@gmail.com> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=93451Acked-by: NDamien Lespiau <damien.lespiau@intel.com> Cc: stable@vger.kernel.org Signed-off-by: NJani Nikula <jani.nikula@intel.com>
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由 Jani Nikula 提交于
skylake_update_primary_plane() did not handle all pixel formats returned by skl_format_to_fourcc(). Handle alpha similar to skl_update_plane(). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89052Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NJani Nikula <jani.nikula@intel.com>
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由 Daniel Vetter 提交于
Where possible right now. Just a small step towards nirvana ... v2: git add. Uggh. Noticed by Imre. Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: NImre Deak <imre.deak@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com>
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由 Daniel Vetter 提交于
At driver load we need to tell the vblank code about the state of the pipes, so that the logic around reject vblank_get when the pipe is off works correctly. Thus far i915 used drm_vblank_off, but one of the side-effects of it is that it also saves the vblank counter. And for that it calls down into the ->get_vblank_counter hook. Which isn't really a good idea when the pipe is off for a few reasons: - With runtime pm the register might not respond. - If the pipe is off some datastructures might not be around or unitialized. The later is what blew up on gen3: We look at intel_crtc->config to compute the vblank counter, and for a disabled pipe at boot-up that's just not there. Thus far this was papered over by a check for intel_crtc->active, but I want to get rid of that (since it's fairly race, vblank hooks are called from all kinds of places). So prep for that by adding a _reset functions which only does what we really need to be done at driver load: Mark the vblank pipe as off, but don't do any vblank counter saving or event flushing - neither of that is required. v2: Clarify the code flow slightly as suggested by Ville. v3: Fix kerneldoc spelling, spotted by Laurent. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> (v2) Acked-by: NDave Airlie <airlied@redhat.com> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com>
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- 14 2月, 2015 5 次提交
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由 Damien Lespiau 提交于
This function is not used outside of intel_display.c since; commit cf4c7c12 Author: Matt Roper <matthew.d.roper@intel.com> Date: Thu Dec 4 10:27:42 2014 -0800 drm/i915: Make all plane disables use 'update_plane' (v5) Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Tvrtko Ursulin 提交于
Let the DRM core know we can handle it. v2: Change to boolean true. (Daniel Vetter) Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Tvrtko Ursulin 提交于
And at the same time replace BUG() with a warning and handle it gracefuly. Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Tvrtko Ursulin 提交于
Also drop the mutex since with universal planes there is always a proper framebuffer around which wraps the underlying bo. Which means tiling is locked down. This was different in the old code which directly took gem handles. The looking though was always cargo-cult since races where not prevented in any way. v2: Unconditionally enforce untiled, because cursors are always untiled. The check for physical or gtt cursor is irrelevant. Also clarify the commit message a bit Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> (v1) Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Tvrtko Ursulin 提交于
And skl only works in execlist mode, not in legacy ring submission. Therefore remove dead code. Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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