- 10 6月, 2017 2 次提交
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由 Tero Kristo 提交于
OMAP AES hw supports AES-GCM mode. This patch adds support for GCM and RFC4106 GCM mode in omap-aes driver. The GCM implementation is mostly written into its own source file, which gets built into the same driver binary as the existing AES support. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> [t-kristo@ti.com: forward port to latest upstream kernel, conversion to use omap-crypto lib and some additional fixes] Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Tero Kristo 提交于
This contains the generic APIs for aligning SG buffers. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 21 4月, 2017 1 次提交
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由 Krzysztof Kozlowski 提交于
Replace existing hw_ranndom/exynos-rng driver with a new, reworked one. This is a driver for pseudo random number generator block which on Exynos4 chipsets must be seeded with some value. On newer Exynos5420 chipsets it might seed itself from true random number generator block but this is not implemented yet. New driver is a complete rework to use the crypto ALGAPI instead of hw_random API. Rationale for the change: 1. hw_random interface is for true RNG devices. 2. The old driver was seeding itself with jiffies which is not a reliable source for randomness. 3. Device generates five random 32-bit numbers in each pass but old driver was returning only one 32-bit number thus its performance was reduced. Compatibility with DeviceTree bindings is preserved. New driver does not use runtime power management but manually enables and disables the clock when needed. This is preferred approach because using runtime PM just to toggle clock is huge overhead. Another difference is reseeding itself with generated random data periodically and during resuming from system suspend (previously driver was re-seeding itself again with jiffies). Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org> Reviewed-by: NStephan Müller <smueller@chronox.de> Reviewed-by: NPrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> Reviewed-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 05 4月, 2017 1 次提交
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由 Fabien DESSENNE 提交于
This module registers a CRC32 ("Ethernet") and a CRC32C (Castagnoli) algorithm that make use of the STMicroelectronics STM32 crypto hardware. Theses algorithms are compatible with the little-endian generic ones. Both algorithms use ~0 as default seed (key). With CRC32C the output is xored with ~0. Using TCRYPT CRC32C speed test, this shows up to 900% speedup compared to the crc32c-generic algorithm. Signed-off-by: NFabien Dessenne <fabien.dessenne@st.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 09 3月, 2017 1 次提交
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由 Mahipal Challa 提交于
Add a driver for the ZIP engine found on Cavium ThunderX SOCs. The ZIP engine supports hardware accelerated compression and decompression. It includes 2 independent ZIP cores and supports: - DEFLATE compression and decompression (RFC 1951) - LZS compression and decompression (RFC 2395 and ANSI X3.241-1994) - ADLER32 and CRC32 checksums for ZLIB (RFC 1950) and GZIP (RFC 1952) The ZIP engine is presented as a PCI device. It supports DMA and scatter-gather. Signed-off-by: NMahipal Challa <Mahipal.Challa@cavium.com> Signed-off-by: NJan Glauber <jglauber@cavium.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 27 2月, 2017 2 次提交
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由 Geert Uytterhoeven 提交于
If NO_DMA=y: ERROR: "bad_dma_ops" [drivers/crypto/mediatek/mtk-crypto.ko] undefined! Add a dependency on HAS_DMA to fix this. Fixes: 7dee9f61 ("crypto: mediatek - remove ARM dependencies") Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Geert Uytterhoeven 提交于
If NO_DMA=y: ERROR: "bad_dma_ops" [drivers/crypto/atmel-tdes.ko] undefined! ERROR: "bad_dma_ops" [drivers/crypto/atmel-sha.ko] undefined! Add dependencies on HAS_DMA to fix this. Fixes: ceb4afb3 ("crypto: atmel - refine Kconfig dependencies") Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 24 2月, 2017 1 次提交
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由 Martin Schwidefsky 提交于
This patch introduces a new in-kernel-crypto blockcipher called 'paes' which implements AES with protected keys. The paes blockcipher can be used similar to the aes blockcipher but uses secure key material to derive the working protected key and so offers an encryption implementation where never a clear key value is exposed in memory. The paes module is only available for the s390 platform providing a minimal hardware support of CPACF enabled with at least MSA level 3. Upon module initialization these requirements are checked. Includes additional contribution from Harald Freudenberger. Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
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- 23 2月, 2017 2 次提交
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由 Harald Freudenberger 提交于
This patch introcudes a new kernel module pkey which is providing protected key handling and management functions. The pkey API is available within the kernel for other s390 specific code to create and manage protected keys. Additionally the functions are exported to user space via IOCTL calls. The implementation makes extensive use of functions provided by the zcrypt device driver. For generating protected keys from secure keys there is also a CEX coprocessor card needed. Signed-off-by: NHarald Freudenberger <freude@linux.vnet.ibm.com> Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
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由 Harald Freudenberger 提交于
The CONFIG_ZCRYPT Kconfig entry in drivers/crypto showed outdated hardware whereas the latest cards where missing. Reworked the text to reflect the current abilities of the zcrypt device driver. Signed-off-by: NHarald Freudenberger <freude@linux.vnet.ibm.com> Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
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- 11 2月, 2017 3 次提交
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由 Rob Rice 提交于
Add Broadcom Secure Processing Unit (SPU) crypto driver for SPU hardware crypto offload. The driver supports ablkcipher, ahash, and aead symmetric crypto operations. Signed-off-by: NSteve Lin <steven.lin1@broadcom.com> Signed-off-by: NRob Rice <rob.rice@broadcom.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 George Cherian 提交于
Add the CPT options in crypto Kconfig and update the crypto Makefile Update the MAINTAINERS file too. Signed-off-by: NGeorge Cherian <george.cherian@cavium.com> Reviewed-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Arnd Bergmann 提交于
With the new authenc support, we get a harmless Kconfig warning: warning: (CRYPTO_DEV_ATMEL_AUTHENC) selects CRYPTO_DEV_ATMEL_SHA which has unmet direct dependencies (CRYPTO && CRYPTO_HW && ARCH_AT91) The problem is that each of the options has slightly different dependencies, although they all seem to want the same thing: allow building for real AT91 targets that actually have the hardware, and possibly for compile testing. This makes all four options consistent: instead of depending on a particular dmaengine implementation, we depend on the ARM platform, CONFIG_COMPILE_TEST as an alternative when that is turned off. This makes the 'select' statements work correctly. Fixes: 89a82ef8 ("crypto: atmel-authenc - add support to authenc(hmac(shaX), Y(aes)) modes") Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 03 2月, 2017 1 次提交
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由 Cyrille Pitchen 提交于
This patchs allows to combine the AES and SHA hardware accelerators on some Atmel SoCs. Doing so, AES blocks are only written to/read from the AES hardware. Those blocks are also transferred from the AES to the SHA accelerator internally, without additionnal accesses to the system busses. Hence, the AES and SHA accelerators work in parallel to process all the data blocks, instead of serializing the process by (de)crypting those blocks first then authenticating them after like the generic crypto/authenc.c driver does. Of course, both the AES and SHA hardware accelerators need to be available before we can start to process the data blocks. Hence we use their crypto request queue to synchronize both drivers. Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 23 1月, 2017 1 次提交
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由 Ryder Lee 提交于
This patch adds support to the GCM mode. Signed-off-by: NRyder Lee <ryder.lee@mediatek.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 13 1月, 2017 2 次提交
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由 Arnd Bergmann 提交于
Building the mediatek driver on an older ARM architecture results in a harmless warning: warning: (ARCH_OMAP2PLUS_TYPICAL && CRYPTO_DEV_MEDIATEK) selects NEON which has unmet direct dependencies (VFPv3 && CPU_V7) We could add an explicit dependency on CPU_V7, but it seems nicer to open up the build to additional configurations. This replaces the ARM optimized algorithm selection with the normal one that all other drivers use, and that in turn lets us relax the dependency on ARM and drop a number of the unrelated 'select' statements. Obviously a real user would still select those other optimized drivers as a fallback, but as there is no strict dependency, we can leave that up to the user. Fixes: 785e5c61 ("crypto: mediatek - Add crypto driver support for some MediaTek chips") Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Javier Martinez Canillas 提交于
Driver only has runtime but no build time dependency with ARCH_PICOXCELL. So it can be built for testing purposes if COMPILE_TEST option is enabled. This is useful to have more build coverage and make sure that the driver is not affected by changes that could cause build regressions. Suggested-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com> Acked-by: NJamie Iles <jamie@jamieiles.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 27 12月, 2016 1 次提交
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由 Ryder Lee 提交于
This adds support for the MediaTek hardware accelerator on mt7623/mt2701/mt8521p SoC. This driver currently implement: - SHA1 and SHA2 family(HMAC) hash algorithms. - AES block cipher in CBC/ECB mode with 128/196/256 bits keys. Signed-off-by: NRyder Lee <ryder.lee@mediatek.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 16 12月, 2016 1 次提交
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由 Gonglei 提交于
This patch introduces virtio-crypto driver for Linux Kernel. The virtio crypto device is a virtual cryptography device as well as a kind of virtual hardware accelerator for virtual machines. The encryption anddecryption requests are placed in the data queue and are ultimately handled by thebackend crypto accelerators. The second queue is the control queue used to create or destroy sessions for symmetric algorithms and will control some advanced features in the future. The virtio crypto device provides the following cryptoservices: CIPHER, MAC, HASH, and AEAD. For more information about virtio-crypto device, please see: http://qemu-project.org/Features/VirtioCrypto CC: Michael S. Tsirkin <mst@redhat.com> CC: Cornelia Huck <cornelia.huck@de.ibm.com> CC: Stefan Hajnoczi <stefanha@redhat.com> CC: Herbert Xu <herbert@gondor.apana.org.au> CC: Halil Pasic <pasic@linux.vnet.ibm.com> CC: David S. Miller <davem@davemloft.net> CC: Zeng Xin <xin.zeng@intel.com> Signed-off-by: NGonglei <arei.gonglei@huawei.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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- 13 9月, 2016 1 次提交
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由 Lokesh Vutla 提交于
As setting up the DMA operations is quite costly, add software fallback support for requests smaller than 200 bytes. This change gives some 10% extra performance in ipsec use case. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> [t-kristo@ti.com: udpated against latest upstream, to use skcipher mainly] Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 19 8月, 2016 1 次提交
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由 Hariprasad Shenai 提交于
Adds the config entry for the Chelsio Crypto Driver, Makefile changes for the same. Signed-off-by: NAtul Gupta <atul.gupta@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 15 6月, 2016 1 次提交
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由 Hendrik Brueckner 提交于
Add a crypto API module to access the vector extension based CRC-32 implementations. Users can request the optimized implementation through the shash crypto API interface. Signed-off-by: NHendrik Brueckner <brueckner@linux.vnet.ibm.com> Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
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- 03 5月, 2016 1 次提交
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由 Baolin Wang 提交于
Since the crypto engine framework had been merged, thus this patch integrates with the newly added crypto engine framework to make the crypto hardware engine under utilized as each block needs to be processed before the crypto hardware can start working on the next block. The crypto engine framework can manage and process the requests automatically, so remove the 'queue' and 'queue_task' things in omap des driver. Signed-off-by: NBaolin <baolin.wang@linaro.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 20 4月, 2016 1 次提交
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由 Christian Lamparter 提交于
This patch integrates the ppc4xx-rng driver into the existing crypto4xx. This is because the true random number generator is controlled and part of the security core. Signed-off-by: NChristian Lamparter <chunkeey@googlemail.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 15 4月, 2016 1 次提交
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由 Steffen Trumtrar 提交于
According to the Freescale GPL driver code, there are two different Security Controller (SCC) versions: SCC and SCC2. The SCC is found on older i.MX SoCs, e.g. the i.MX25. This is the version implemented and tested here. As there is no publicly available documentation for this IP core, all information about this unit is gathered from the GPL'ed driver from Freescale. Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 05 4月, 2016 2 次提交
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由 Krzysztof Kozlowski 提交于
Get some build coverage of S5P/Exynos AES H/W acceleration driver. Driver uses DMA and devm_ioremap_resource() so add DMA and IOMEM dependencies for the compile testing. Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: NVladimir Zapolskiy <vz@mleia.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Peter Meerwald 提交于
Signed-off-by: NPeter Meerwald <pmeerw@pmeerw.net> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 28 2月, 2016 1 次提交
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由 Zain Wang 提交于
Add md5 sha1 sha256 support for crypto engine in rk3288. Signed-off-by: NZain Wang <zain.wang@rock-chips.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 06 2月, 2016 1 次提交
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由 Andre Przywara 提交于
The driver for the sunxi-ss crypto engine is not entirely 64-bit safe, compilation on arm64 spits some warnings. The proper fix was deemed to involved [1], so since 64-bit SoCs won't have this IP block we just disable this driver for 64-bit. [1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/399988.html (and the reply) Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Acked-by: NCorentin LABBE <clabbe.montjoie@gmail.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 01 2月, 2016 1 次提交
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由 Baolin Wang 提交于
Integrate with the newly added crypto engine to make the crypto hardware engine underutilized as each block needs to be processed before the crypto hardware can start working on the next block. The requests from dm-crypt will be listed into engine queue and processed by engine automatically, so remove the 'queue' and 'queue_task' things in omap aes driver. Signed-off-by: NBaolin Wang <baolin.wang@linaro.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 18 1月, 2016 1 次提交
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由 Geert Uytterhoeven 提交于
If NO_DMA=y: ERROR: "dma_unmap_sg" [drivers/crypto/atmel-aes.ko] undefined! ERROR: "dma_map_sg" [drivers/crypto/atmel-aes.ko] undefined! Add a dependency on HAS_DMA to fix this. Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 23 12月, 2015 1 次提交
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由 Cyrille Pitchen 提交于
This patch adds support to the GCM mode. Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 22 12月, 2015 1 次提交
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由 LABBE Corentin 提交于
Precalculated hash for empty message are now present in hash headers. This patch just use them. Signed-off-by: NLABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 27 11月, 2015 1 次提交
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由 Zain Wang 提交于
Crypto driver support: ecb(aes) cbc(aes) ecb(des) cbc(des) ecb(des3_ede) cbc(des3_ede) You can alloc tags above in your case. And other algorithms and platforms will be added later on. Signed-off-by: NZain Wang <zain.wang@rock-chips.com> Tested-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 23 11月, 2015 1 次提交
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由 Arnd Bergmann 提交于
The Atmel at91 crypto driver unconditionally selects AT_HDMAC, which results in a Kconfig warning if that driver is not enabled: warning: (CRYPTO_DEV_ATMEL_AES) selects AT_HDMAC which has unmet direct dependencies (DMADEVICES && ARCH_AT91) The crypto driver itself does not actually have a dependency on a particular dma engine, other than this being the one that is used in at91. Removing the 'select' gets rid of the warning, but can cause the driver to be unusable if the HDMAC is not enabled at the same time. To work around that, this patch clarifies the runtime dependency to be 'AT_HDMAC || AT_XDMAC', but adds an alternative for COMPILE_TEST, which lets the driver get build on all systems. The ARCH_AT91 dependency is implied by AT_XDMAC || AT_HDMAC now and no longer needs to be listed separately. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 14 10月, 2015 1 次提交
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由 Arnd Bergmann 提交于
The mxs-dcp driver relies on the stmp_reset_block() helper function, which is provided by CONFIG_STMP_DEVICE. This symbol is always set on MXS, but the driver can now also be built for MXC (i.MX6), which results in a built error if no other driver selects STMP_DEVICE: drivers/built-in.o: In function `mxs_dcp_probe': vf610-ocotp.c:(.text+0x3df302): undefined reference to `stmp_reset_block' This adds the 'select', like all other stmp drivers have it. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Fixes: a2712e6c ("crypto: mxs-dcp - Allow MXS_DCP to be used on MX6SL") Acked-by: NMarek Vasut <marex@denx.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 08 10月, 2015 1 次提交
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由 Tom Lendacky 提交于
The CCP is meant to be more of an offload engine than an accelerator engine. To avoid any confusion, change references to accelerator to offload. Signed-off-by: NTom Lendacky <thomas.lendacky@amd.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 21 9月, 2015 1 次提交
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由 Fabio Estevam 提交于
MX6SL has the same DCP crypto block as in MX23/MX28, so allow it to be built for ARCH_MXC. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 10 9月, 2015 1 次提交
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由 Michael Ellerman 提交于
This code uses FP (floating point), Altivec and VSX (Vector-Scalar Extension). It can just depend on CONFIG_VSX though, because that already depends on FP and Altivec. Otherwise we get lots of link errors such as: drivers/built-in.o: In function `.p8_aes_setkey': aes.c:(.text+0x2d325c): undefined reference to `.enable_kernel_altivec' aes.c:(.text+0x2d326c): undefined reference to `.enable_kernel_vsx' Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 20 7月, 2015 1 次提交
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由 LABBE Corentin 提交于
Add support for the Security System included in Allwinner SoC A20. The Security System is a hardware cryptographic accelerator that support: - MD5 and SHA1 hash algorithms - AES block cipher in CBC/ECB mode with 128/196/256bits keys. - DES and 3DES block cipher in CBC/ECB mode Signed-off-by: NLABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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