Now that the Armada 370/XP platform has gained proper integration with
the clock framework, we add clk support in the Marvell Armada 370/XP
Ethernet driver.

Since the existing Device Tree binding that exposes a
'clock-frequency' property has never been exposed in any stable kernel
release, we take the freedom of removing this property to replace it
with the standard 'clocks' clock pointer property.

The Device Tree binding documentation is updated accordingly.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

This patch contains a new network driver for the network unit of the
ARM Marvell Armada 370 and the Armada XP. Both SoCs use the PJ4B
processor, a Marvell-developed ARM core that implements the ARMv7
instruction set.

Compared to previous ARM Marvell SoCs (Kirkwood, Orion, Discovery),
the network unit in Armada 370 and Armada XP is highly different. This
is the reason why this new 'mvneta' driver is needed, while the older
ARM Marvell SoCs use the 'mv643xx_eth' driver.

Here is an overview of the most important hardware changes that
require a new, specific, driver for the network unit of Armada 370/XP:

 - The new network unit has a completely different design and layout
   for the RX and TX descriptors. They are now organized as a simple
   array (each RX and TX queue has base address and size of this
   array) rather than a linked list as in the old SoCs.

 - The new network unit has a different RXQ and TXQ management: this
   management is done using special read/write counter registers,
   while in the Old SocS, it was done using the Ownership bit in RX
   and TX descriptors.

 - The new network unit has different interrupt registers

 - The new network unit way of cleaning of interrupts is not done by
   writing to the cause register, but by updating per-queue counters

 - The new network unit has different GMAC registers (link, speed,
   duplex configuration) and different WRR registers.

 - The new network unit has lots of new units like PnC (Parser and
   Classifier), PMT, BM (Memory Buffer Management), xPON, and more.

The driver proposed in the current patch only handles the basic
features. Additional hardware features will progressively be supported
as needed.

This code has originally been written by Rami Rosen
<rosenr@marvell.com>, and then reviewed and cleaned up by Thomas
Petazzoni <thomas.petazzoni@free-electrons.com>.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NDavid S. Miller <davem@davemloft.net>