1. 05 8月, 2015 1 次提交
  2. 18 12月, 2013 1 次提交
  3. 09 12月, 2013 1 次提交
  4. 14 10月, 2013 1 次提交
  5. 30 3月, 2013 1 次提交
    • C
      ARM: PL011: Add support for Rx DMA buffer polling. · cb06ff10
      Chanho Min 提交于
      In DMA support, The received data is not pushed to tty until the DMA buffer
      is filled. But some megabyte rate chips such as BT expect fast response and
      data should be pushed immediately. In order to fix this issue, We suggest
      the use of the timer for polling DMA buffer.
      In our test, no data loss occurred at high-baudrate as compared with interrupt-
      driven (We tested with 3Mbps).
      We changes:
      
      - We add timer for polling. If we set poll_timer to 10, every 10ms,
       timer handler checks the residue in the dma buffer and transfer data
       to the tty. Also, last_residue is updated for the next polling.
      
      - poll_timeout is used to prevent the timer's system cost.
        If poll_timeout is set to 3000 and no data is received in 3 seconds,
        we inactivate poll timer and driver falls back to interrupt-driven.
        When data is received again in FIFO and UART irq is occurred, we switch
        back to DMA mode and start polling.
      
      - We use consistent DMA mappings to avoid from the frequent cache operation
        of the timer function for default.
      
      - pl011_dma_rx_chars is modified. the pending size is recalculated because
        data can be taken by polling.
      
      - the polling time is adjusted if dma rx poll is enabled but no rate is
        specified. Ideal polling interval to push 1 character at every interval
        is the reciprocal of 'baud rate / 10 line bits per character / 1000 ms
        per sec'. But It is very aggressive to system. Experimentally,
       '10000000 / baud' is suitable to receive dozens of characters. the poll rate
       can be specified statically by dma_rx_poll_rate of the platform data as well.
      
      Changes compared to v1:
       - Use of consistent DMA mappings.
       - Added dma_rx_poll_rate in platform data to specify the polling interval.
       - Added dma_rx_poll_timeout in platform data to specify the polling timeout.
      
      Changes compared to v2:
       - Use of consistent DMA mappings for default.
       - Added dma_rx_poll_enable in platform data to adjust the polling time
         according to the baud rate.
       - remove unnecessary lock from the polling function.
      Signed-off-by: NChanho Min <chanho.min@lge.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      cb06ff10
  6. 11 9月, 2012 1 次提交
  7. 24 2月, 2012 1 次提交
  8. 09 7月, 2011 1 次提交
    • S
      amba pl011: workaround for uart registers lockup · def90f42
      Shreshtha Kumar Sahu 提交于
      This workaround aims to break the deadlock situation
      which raises during continuous transfer of data for long
      duration over uart with hardware flow control. It is
      observed that CTS interrupt cannot be cleared in uart
      interrupt register (ICR). Hence further transfer over
      uart gets blocked.
      
      It is seen that during such deadlock condition ICR
      don't get cleared even on multiple write. This leads
      pass_counter to decrease and finally reach zero. This
      can be taken as trigger point to run this UART_BT_WA.
      
      Workaround backups the register configuration, does soft
      reset of UART using BIT-0 of PRCC_K_SOFTRST_SET/CLEAR
      registers and restores the registers.
      
      This patch also provides support for uart init and exit
      function calls if present.
      Signed-off-by: NShreshtha Kumar Sahu <shreshthakumar.sahu@stericsson.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      def90f42
  9. 17 6月, 2011 1 次提交
    • S
      amba pl011: workaround for uart registers lockup · c16d51a3
      Shreshtha Kumar Sahu 提交于
      This workaround aims to break the deadlock situation
      which raises during continuous transfer of data for long
      duration over uart with hardware flow control. It is
      observed that CTS interrupt cannot be cleared in uart
      interrupt register (ICR). Hence further transfer over
      uart gets blocked.
      
      It is seen that during such deadlock condition ICR
      don't get cleared even on multiple write. This leads
      pass_counter to decrease and finally reach zero. This
      can be taken as trigger point to run this UART_BT_WA.
      
      Workaround backups the register configuration, does soft
      reset of UART using BIT-0 of PRCC_K_SOFTRST_SET/CLEAR
      registers and restores the registers.
      
      This patch also provides support for uart init and exit
      function calls if present.
      Signed-off-by: NShreshtha Kumar Sahu <shreshthakumar.sahu@stericsson.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      c16d51a3
  10. 06 1月, 2011 2 次提交
    • R
      ARM: PL011: add DMA burst threshold support for ST variants · 38d62436
      Russell King 提交于
      ST Micro variants has some specific dma burst threshold compensation,
      which allows them to make better use of a DMA controller.  Add support
      to set this up.
      
      Based on a patch from Linus Walleij.
      Acked-by: NLinus Walleij <linus.walleij@stericsson.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      38d62436
    • R
      ARM: PL011: Add support for transmit DMA · 68b65f73
      Russell King 提交于
      Add DMA engine support for transmit to the PL011 driver.  Based on a
      patch from Linus Walliej, with the following changes:
      
      - remove RX DMA support.  As PL011 doesn't give us receive timeout
        interrupts, we only get notified of received data when the RX DMA
        has completed.  This rather sucks for interactive use of the TTY.
      
      - remove abuse of completions.  Completions are supposed to be for
        events, not to tell what condition buffers are in.  Replace it with
        a simple 'queued' bool.
      
      - fix locking - it is only safe to access the circular buffer with the
        port lock held.
      
      - only map the DMA buffer when required - if we're ever behind an IOMMU
        this helps keep IOMMU usage down, and also ensures that we're legal
        when we change the scatterlist entry length.
      
      - fix XON/XOFF sending - we must send XON/XOFF characters out as soon
        as possible - waiting for up to 4095 characters in the DMA buffer
        to be sent first is not acceptable.
      
      - fix XON/XOFF receive handling - we need to stop DMA when instructed
        to by the TTY layer, and restart it again when instructed to.  There
        is a subtle problem here: we must not completely empty the circular
        buffer with DMA, otherwise we will not be notified of XON.
      
      - change the 'enable_dma' flag into a 'using DMA' flag, and track
        whether we can use TX DMA by whether the channel pointer is non-NULL.
        This gives us more control over whether we use DMA in the driver.
      
      - we don't need to have the TX DMA buffer continually allocated for
        each port - instead, allocate it when the port starts up, and free
        it when it's shut down.  Update the 'using DMA' flag if we get
        the buffer, and adjust the TTY FIFO size appropriately.
      
      - if we're going to use PIO to send characters, use the existing IRQ
        based functionality rather than reimplementing it.  This also ensures
        we call uart_write_wakeup() at the appropriate time, otherwise we'll
        stall.
      
      - use DMA engine helper functions for type safety.
      
      - fix init when built as a module - we can't have to initcall functions,
        so we must settle on one.  This means we can eliminate the deferred
        DMA initialization.
      
      - there is no need to terminate transfers on a failed prep_slave_sg()
        call - nothing has been setup, so nothing needs to be terminated.
        This avoids a potential deadlock in the DMA engine code
        (tasklet->callback->failed prepare->terminate->tasklet_disable
         which then ends up waiting for the tasklet to finish running.)
      
      - Dan says that the submission callback should not return an error:
        | dma_submit_error() is something I should have removed after commit
        | a0587bcf "ioat1: move descriptor allocation from submit to prep" all
        | errors should be notified by prep failing to return a descriptor
        | handle.  Negative dma_cookie_t values are only returned by the
        | dma_async_memcpy* calls which translate a prep failure into -ENOMEM.
        So remove the error handling at that point.  This also solves the
        potential deadlock mentioned in the previous comment.
      Acked-by: NLinus Walleij <linus.walleij@stericsson.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      68b65f73
  11. 12 10月, 2010 1 次提交
  12. 27 7月, 2010 2 次提交
  13. 07 6月, 2009 1 次提交
  14. 05 6月, 2009 1 次提交
  15. 27 3月, 2006 1 次提交
  16. 07 1月, 2006 1 次提交
  17. 19 11月, 2005 1 次提交
  18. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4