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  1. 05 7月, 2018 4 次提交
  3. 04 7月, 2018 5 次提交
  5. 30 6月, 2018 2 次提交
    • Y
      IB: Improve uverbs_cleanup_ucontext algorithm · 1c77483e
      由 Yishai Hadas 提交于 
      Improve uverbs_cleanup_ucontext algorithm to work properly when the
topology graph of the objects cannot be determined at compile time.  This
is the case with objects created via the devx interface in mlx5.

Typically uverbs objects must be created in a strict topologically sorted
order, so that LIFO ordering will generally cause them to be freed
properly. There are only a few cases (eg memory windows) where objects can
point to things out of the strict LIFO order.

Instead of using an explicit ordering scheme where the HW destroy is not
allowed to fail, go over the list multiple times and allow the destroy
function to fail. If progress halts then a final, desperate, cleanup is
done before leaking the memory. This indicates a driver bug.
Signed-off-by: NYishai Hadas <yishaih@mellanox.com>
Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      1c77483e
    • L
      RDMA/mlx5: Don't leak UARs in case of free fails · 15177999
      由 Leon Romanovsky 提交于 
      The failure in releasing one UAR doesn't mean that we can't continue to
release rest of system pages, so don't return too early.

As part of cleanup, there is no need to print warning if
mlx5_cmd_free_uar() fails because such warning will be printed as part of
mlx5_cmd_exec().
Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      15177999
  7. 28 6月, 2018 1 次提交
  9. 27 6月, 2018 1 次提交
  11. 26 6月, 2018 3 次提交
    • J
      IB/usnic: Update with bug fixes from core code · 43cbd64b
      由 Jason Gunthorpe 提交于 
      usnic has a modified version of the core codes' ib_umem_get() and
related, and the copy misses many of the bug fixes done over the years:

Commit bc3e53f6 ("mm: distinguish between mlocked and pinned pages")
Commit 87773dd5 ("IB: ib_umem_release() should decrement mm->pinned_vm
                      from ib_umem_get")
Commit 8494057a ("IB/uverbs: Prevent integer overflow in ib_umem_get
                      address arithmetic")
Commit 8abaae62 ("IB/core: disallow registering 0-sized memory region")
Commit 66578b0b ("IB/core: don't disallow registering region starting
                      at 0x0")
Commit 53376fed ("RDMA/core: not to set page dirty bit if it's already
                      set.")
Commit 8e907ed4 ("IB/umem: Use the correct mm during ib_umem_release")
Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      43cbd64b
    • Y
      IB/mlx4: Add support for drain SQ & RQ · 1975acd9
      由 Yishai Hadas 提交于 
      This patch follows the logic from ib_core but considers the internal
device state upon executing the involved commands.

Specifically, Upon internal error state modify QP to an error state can
be assumed to be success as each in-progress WR going to be flushed in
error in any case as expected by that modify command.

In addition,
As the drain should never fail the driver makes sure that post_send/recv
will succeed even if the device is already in an internal error state.
As such once the driver will supply the simulated/SW CQEs the CQE for
the drain WR will be handled as well.

In case of an internal error state the CQE for the drain WR may be
completed as part of the main task that handled the error state or by
the task that issued the drain WR.

As the above depends on scheduling the code takes the relevant locks
and actions to make sure that the completion handler for that WR will
always be called after that the post_send/recv were issued but not in
parallel to the other task that handles the error flow.
Signed-off-by: NYishai Hadas <yishaih@mellanox.com>
Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      1975acd9
    • Y
      IB/mlx5: Add support for drain SQ & RQ · d0e84c0a
      由 Yishai Hadas 提交于 
      This patch follows the logic from ib_core but considers the internal
device state upon executing the involved commands.

Specifically,
Upon internal error state modify QP to an error state can be assumed to
be success as each in-progress WR going to be flushed in error in any
case as expected by that modify command.

In addition,
As the drain should never fail the driver makes sure that post_send/recv
will succeed even if the device is already in an internal error state.
As such once the driver will supply the simulated/SW CQEs the CQE for
the drain WR will be handled as well.

In case of an internal error state the CQE for the drain WR may be
completed as part of the main task that handled the error state or by
the task that issued the drain WR.

As the above depends on scheduling the code takes the relevant locks and
actions to make sure that the completion handler for that WR will always
be called after that the post_send/recv were issued but not in parallel
to the other task that handles the error flow.
Signed-off-by: NYishai Hadas <yishaih@mellanox.com>
Reviewed-by: NMax Gurtovoy <maxg@mellanox.com>
Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      d0e84c0a
  13. 22 6月, 2018 8 次提交
  15. 20 6月, 2018 13 次提交
  17. 19 6月, 2018 3 次提交