- 16 12月, 2019 2 次提交
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由 Wolfram Sang 提交于
New datasheets require different and new values for HS400 with 4taps or 8taps. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191203200513.1758-6-wsa+renesas@sang-engineering.comSigned-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
We know now that there won't be Gen3 SoCs with both, SYS-DMAC and internal DMAC. We removed the blacklisting for SYS-DMAC already, so we can remove the whitelisting for internal DMAC, too. This makes adding new SoCs easier. We keep the quirk handling, of course. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191203194859.917-1-wsa@the-dreams.deSigned-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 13 11月, 2019 1 次提交
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由 Biju Das 提交于
This patch adds SDHI support for RZ/G2N (R8A774B1) SoC. Signed-off-by: NBiju Das <biju.das@bp.renesas.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 12 9月, 2019 1 次提交
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由 Yoshihiro Shimoda 提交于
Since this host controller can merge bigger segments if DMA API layer cam merge the segments, this patch adds the flag. Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: NUlf Hansson <ulf.hansson@linaro.org> Signed-off-by: NChristoph Hellwig <hch@lst.de>
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- 15 4月, 2019 2 次提交
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由 Wolfram Sang 提交于
max_req_size is calculated by 'max_blk_size * max_blk_count' in the TMIO core. So, specifying U32_MAX as max_blk_count will overflow this calculation. It will cause no harm in practice because the immense high number will overflow into another immense high number. However, it is not good coding practice, so calculate max_blk_count so that max_req_size will fit into unsigned int on ARM32/64. Thanks to the Renesas BSP team for the bug report! Reported-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
Mostly year updates, but one addition as well. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Reviewed-by: NNiklas Söderlund <niklas.soderlund@ragnatech.se> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 25 2月, 2019 1 次提交
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由 Takeshi Saito 提交于
SCC is used for SDR104/HS200/HS400. We need to change SCC_DT2FF according to the mode. If it is inappropriate, CRC error tends to occur. This adds variable "tap_hs400" for HS400 mode and configures SCC_DT2FF as needed. Signed-off-by: NTakeshi Saito <takeshi.saito.xv@renesas.com> [wsa: rebased to upstream and updated commit message] Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NNiklas Söderlund <niklas.soderlund@ragnatech.se> Tested-by: NMarek Vasut <marek.vasut@gmail.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 17 12月, 2018 4 次提交
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由 Biju Das 提交于
We need r8a774c0 to be whitelisted for SDHI to work on the RZ/G2E, but we don't care about the revision of the SoC, so just whitelist the generic part number. Signed-off-by: NBiju Das <biju.das@bp.renesas.com> Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Niklas Söderlund 提交于
It was though all ES revisions of H3 and M3-W SoCs required the TMIO_MMC_HAVE_4TAP_HS400 flag. Recent datasheet updates tells us this is not true, only early ES revisions of the SoC do. Since quirk matching based on ES revisions is now used to handle the flag it's possible to align all Gen3 compatibility properties. This will allow later ES revisions of H3 and M3-W to use the correct 8-tap HS400 mode. Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Marek Vasut 提交于
Whitelist R8A77990 E3 SoC in the SDHI driver. The SDHI core present in the SoC is an 8tap variant of the Gen3 SDHI core. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Simon Horman <horms+renesas@verge.net.au> Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: linux-renesas-soc@vger.kernel.org Reviewed-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chris Brandt 提交于
The SDHI/MMC controller in the RZ/A2 is almost the same as R-Car gen3, but with some minor differences. Signed-off-by: NChris Brandt <chris.brandt@renesas.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 15 10月, 2018 2 次提交
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由 Masahiro Yamada 提交于
host->chan_{rx,tx} represents the DMA capability of the platform. Even if DMA is supported, there are cases where we want to use PIO, for example, data length is short enough as commit 5f52c355 ("mmc: tmio: use PIO for short transfers") mentioned. Regarding the hardware control flow, we are interested in whether DMA is currently enabled or not, instead of whether the platform has the DMA capability. Hence, the several conditionals in tmio_mmc_core.c end up with checking host->chan_{rx,tx} and !host->force_pio. This is not nice. Let's flip the flag host->force_pio into host->dma_on. host->dma_on represents whether the DMA is currently enabled or not. This flag is set false in the beginning of each command, then should be set true by tmio_mmc_start_dma() when the DMA is turned on. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Fabrizio Castro 提交于
The RZ/G1C (a.k.a. R8A77470) comes with three SDHI interfaces, SDHI0 and SDHI2 are compatible with the R-Car Gen2 SDHIs, SDHI1 is compatible with R-Car Gen3 SDHIs and it can be used as eMMC as well. This patch adds driver compatibility, and makes sure both drivers get compiled for the R8A77470. Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: NBiju Das <biju.das@bp.renesas.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 08 10月, 2018 5 次提交
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由 Niklas Söderlund 提交于
Fix warning when running with CONFIG_DMA_API_DEBUG_SG=y by allocating a device_dma_parameters structure and filling in the max segment size. The size used is the result of a discussion with Renesas hardware engineers and unfortunately not found in the datasheet. renesas_sdhi_internal_dmac ee140000.sd: DMA-API: mapping sg segment longer than device claims to support [len=126976] [max=65536] Reported-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se> [wsa: simplified some logic after validating intended dma_parms life cycle and added comment] Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Sergei Shtylyov 提交于
I've successfully tested eMMC on the V3H Starter Kit board and since the R8A77970 SoC has a single SDHI core, it can't be a subject to the known RX DMA errata. Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Sergei Shtylyov 提交于
Remove the stray underscore in the DM_CM_DTRAN_MODE.BUS_WIDTH register field name and fix the typo in the comment of the #define DTRAN_MODE_CH_NUM_CH1. Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Fabrizio Castro 提交于
We need r8a774a1 to be whitelisted for SDHI to work on the RZ/G2M, but we don't care about the revision of the SoC, so just whitelist the generic part number. Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: NBiju Das <biju.das@bp.renesas.com> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 23 8月, 2018 2 次提交
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由 Sergei Shtylyov 提交于
I have encountered an interrupt storm during the eMMC chip probing (and the chip finally didn't get detected). It turned out that U-Boot left the SDHI DMA interrupts enabled while the Linux driver didn't use those. Masking those interrupts in renesas_sdhi_internal_dmac_request_dma() gets rid of both issues... Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Fixes: 2a68ea78 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC") Cc: stable@vger.kernel.org # v4.14+ Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Sergei Shtylyov 提交于
The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS. Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Fixes: 2a68ea78 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC") Cc: stable@vger.kernel.org # v4.14+ Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 16 7月, 2018 1 次提交
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由 Masaharu Hayakawa 提交于
This patch adds processing for selecting HS400 mode. Signed-off-by: NMasaharu Hayakawa <masaharu.hayakawa.ry@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 02 7月, 2018 2 次提交
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由 Yoshihiro Shimoda 提交于
This patch is fixes an issue that the SDHI_INTERNAL_DMAC_RX_IN_USE flag cannot be cleared because tmio_mmc_core sets the host->data to NULL before the tmio_mmc_core calls tmio_mmc_abort_dma(). So, this patch clears the SDHI_INTERNAL_DMAC_RX_IN_USE in the renesas_sdhi_internal_dmac_abort_dma() anyway. This doesn't cause any side effects. Fixes: 0cbc94da ("mmc: renesas_sdhi_internal_dmac: limit DMA RX for old SoCs") Cc: <stable@vger.kernel.org> # v4.17+ Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Yoshihiro Shimoda 提交于
This patch fixes an issue that lacks the dma_unmap_sg() calling in the error patch of renesas_sdhi_internal_dmac_start_dma(). Fixes: 0cbc94da ("mmc: renesas_sdhi_internal_dmac: limit DMA RX for old SoCs") Cc: <stable@vger.kernel.org> # v4.17+ Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 04 6月, 2018 1 次提交
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由 Wolfram Sang 提交于
This reverts commit e060d376 ("mmc: renesas_sdhi: fix WP detection") and adds some code to really fix the regressions. It was missed so far that Renesas R-Car instantiations of SDHI chose to disable internal WP and used the existence of "wp-gpios" to en/disable WP at all. With the first refactoring by Yamada-san with commit 2ad1db05 ("mmc: renesas_sdhi: use MMC_CAP2_NO_WRITE_PROTECT instead of TMIO own flag"), WP was always disabled even when GPIOs were present. With Wolfram's first fix which gets now reverted, GPIOs were honored. But when not available, the fallback was to internal WP and not to disabled WP. This caused wrong WP status on uSD card slots. Restore the old behaviour now. By default, WP is disabled. When a GPIO is found, the GPIO re-enables WP. We will think about possible better ways to handle this in the future. Tested on a previously regressing Renesas Lager board (H2) and a still working Renesas Salvator-X board (M3-W). Reported-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Cc: stable@vger.kernel.org # v4.17+ Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 21 5月, 2018 1 次提交
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由 Masaharu Hayakawa 提交于
This patch adds r8a77965 support in SDHI. Signed-off-by: NMasaharu Hayakawa <masaharu.hayakawa.ry@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Tested-by: NSimon Horman <horms+renesas@verge.net.au> Tested-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 02 5月, 2018 5 次提交
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由 Sergei Shtylyov 提交于
I've successfully tested eMMC on R8A77980/Condor. R8A77980 has a single SDHI core anyway, so can't be a subject of the known RX DMA errata... Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
The WARN can never trigger because we limited the max_seg number in renesas_sdhi_of_data already. Remove it and update the comment. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
Whitelisting every ES version does not scale. So, we whitelist whole SoCs independent of ES version. If we need specific handling for an ES version, we put it to the front, so it will be matched first. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Tested-by: NNguyen Viet Dung <dung.nguyen.aj@renesas.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Masaharu Hayakawa 提交于
Sometimes sg->offset is not used for buffer addresses allocated by dma_map_sg(), so alignment checks should be done on the allocated buffer addresses. Delete the alignment check for sg->offset that is done before dma_map_sg(). Instead, it performs the alignment check for sg->dma_address after dma_map_sg(). Signed-off-by: NMasaharu Hayakawa <masaharu.hayakawa.ry@renesas.com> [Niklas: broke this commit in two and tidied small style issue] Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se> [rebased to mmc/next] Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Niklas Söderlund 提交于
Instead of directly accessing the members of struct scatterlist use the helpers mmc_get_dma_dir() and sg_dma_address() in renesas_sdhi_internal_dmac_start_dma(). Based on previous work by Masaharu Hayakawa. Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se> [rebased to mmc/next] Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 19 4月, 2018 1 次提交
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由 Wolfram Sang 提交于
Early revisions of certain SoCs cannot do multiple DMA RX streams in parallel. To avoid data corruption, only allow one DMA RX channel and fall back to PIO, if needed. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: NNguyen Viet Dung <dung.nguyen.aj@renesas.com> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Cc: stable@vger.kernel.org Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 15 3月, 2018 1 次提交
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由 Wolfram Sang 提交于
Commit "mmc: renesas_sdhi: use MMC_CAP2_NO_WRITE_PROTECT instead of TMIO own flag" activated MMC_CAP2_NO_WRITE_PROTECT for Renesas SDHI which incorrectly disabled WP altogether instead of only disabling the internal mechanism. Since the whole WP handling has been reworked, we can simply disable this capability to re-enable WP GPIOs. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 05 3月, 2018 2 次提交
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由 Masahiro Yamada 提交于
As far as I tested the IP on UniPhier SoCs, TMIO_STAT_{RXRDY,TXRQ} are asserted for DMA mode as well as for PIO. I need to disable the those IRQs in dma_ops->start hook, otherwise the DMA transfer fails with the following error message: PIO IRQ in DMA mode! Renesas chips are the same cases since I see their dma_ops->start hooks explicitly clear TMIO_STAT_{RXRDY,TXRQ} (with nice comment!). If we do this sanity check in TMIO MMC core, RXRDY/TXRQ handling should be entirely moved to the core. tmio_mmc_cmd_irq() will be a suitable place to disable them. The probe function sets TMIO_MASK_{READOP,WRITEOP} but this is odd. /* Unmask the IRQs we want to know about */ if (!_host->chan_rx) irq_mask |= TMIO_MASK_READOP; if (!_host->chan_tx) irq_mask |= TMIO_MASK_WRITEOP; At this point, _host->{chan_rx,chan_tx} are _always_ NULL because tmio_mmc_request_dma() is called after this code. Consequently, TMIO_MASK_{READOP,WRITEOP} are set here whether DMA is used or not. Remove this pointless code. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
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由 Masahiro Yamada 提交于
TMIO_MMC_WRPROTECT_DISABLE is equivalent to MMC_CAP2_NO_WRITE_PROTECT. The flag is propagated as follows: renesas_sdhi_of_data::capabilities2 -> tmio_mmc_data::capabilities2 -> mmc_host::caps2 Only the difference is the TMIO_... makes tmio_mmc_get_ro() return 0 (i.e. it does not affect mmc_gpio_get_ro() at all), while MMC_CAP2_... returns 0 before calling ->get_ro() hook (i.e. it affects both IP own logic and GPIO detection). The TMIO MMC drivers do not set-up gpio_ro by themselves. Only the possibility, if any, would be DT specifies "wp-gpios" property, and gpio_ro is set by mmc_gpiod_request_ro() called from mmc_of_parse(). However, it does not make sense to specify "wp-gpios" property and TMIO_MMC_WRPROTECT_DISABLE at the same time. I checked under arch/arm/boot/dts/ and arch/arm64/boot/dts/renesas/, and I did not see any Renesas boards with "wp-gpios". So, this conversion should be safe. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org> Tested-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
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- 19 12月, 2017 2 次提交
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由 Masahiro Yamada 提交于
struct tmio_mmc_host has "dma_dataend" and "dma_complete", but in fact, they are Renesas private data. Move them to renesas_sdhi.h Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Masahiro Yamada 提交于
struct tmio_mmc_dma looks like TMIO core data, but in fact, Renesas private data. Move it to renesas_sdhi.h (probably, it is better to rename it to renesas_sdhi_dma, or squash it into struct renesas_sdhi). I also moved struct renesas_sdhi and host_to_priv() to that header because they are necessary to convert the tmio_mmc_host pointer into the renesas_sdhi pointer. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 11 12月, 2017 1 次提交
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由 Ulrich Hecht 提交于
Whitelists for internal DMAC implementation. Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org> Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
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- 30 10月, 2017 1 次提交
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由 Simon Horman 提交于
Implement fallback compatibility strings for R-Car Gen 1, 2 and 3. In the case of Renesas R-Car hardware we know that there are generations of SoCs, f.e. Gen 1 and 2. But beyond that its not clear what the relationship between IP blocks might be. For example, I believe that r8a7790 is older than r8a7791 but that doesn't imply that the latter is a descendant of the former or vice versa. We can, however, by examining the documentation and behaviour of the hardware at run-time observe that the current driver implementation appears to be compatible with the IP blocks on SoCs within a given generation. For the above reasons and convenience when enabling new SoCs a per-generation fallback compatibility string scheme is being adopted for drivers for Renesas SoCs. Also, improve readability by listing the shmobile fallback compatibility string after the more-specific compatibility strings they provide a fallback for. Signed-off-by: NSimon Horman <horms+renesas@verge.net.au> Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 20 10月, 2017 1 次提交
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由 Yoshihiro Shimoda 提交于
Since this driver checks if the return value of dma_map_sg() is minus or not and keeps to enable the DMAC, it may cause kernel panic when the dma_map_sg() returns 0. So, this patch fixes the issue. Reported-by: NDirk Behme <dirk.behme@de.bosch.com> Fixes: 2a68ea78 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC") Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 30 8月, 2017 1 次提交
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由 Wolfram Sang 提交于
There is one SDHI instance on Gen2 which does not have the CBSY bit. So, turn CBSY usage into an extra flag and set it accordingly. This has the additional advantage that we can also set it for other incarnations later. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: NChris Brandt <Chris.Brandt@renesas.com> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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