1. 14 1月, 2020 3 次提交
  2. 09 1月, 2020 1 次提交
  3. 06 1月, 2020 1 次提交
  4. 05 1月, 2020 1 次提交
    • P
      Documentation: riscv: add patch acceptance guidelines · 0e194d9d
      Paul Walmsley 提交于
      Formalize, in kernel documentation, the patch acceptance policy for
      arch/riscv.  In summary, it states that as maintainers, we plan to
      only accept patches for new modules or extensions that have been
      frozen or ratified by the RISC-V Foundation.
      
      We've been following these guidelines for the past few months.  In the
      meantime, we've received quite a bit of feedback that it would be
      helpful to have these guidelines formally documented.
      
      Based on a suggestion from Matthew Wilcox, we also add a link to this
      file to Documentation/process/index.rst, to make this document easier
      to find.  The format of this document has also been changed to align
      to the format outlined in the maintainer entry profiles, in accordance
      with comments from Jon Corbet and Dan Williams.
      Signed-off-by: NPaul Walmsley <paul.walmsley@sifive.com>
      Reviewed-by: NPalmer Dabbelt <palmerdabbelt@google.com>
      Cc: Palmer Dabbelt <palmer@dabbelt.com>
      Cc: Albert Ou <aou@eecs.berkeley.edu>
      Cc: Krste Asanovic <krste@berkeley.edu>
      Cc: Andrew Waterman <waterman@eecs.berkeley.edu>
      Cc: Matthew Wilcox <willy@infradead.org>
      Cc: Dan Williams <dan.j.williams@intel.com>
      Cc: Jonathan Corbet <corbet@lwn.net>
      0e194d9d
  5. 03 1月, 2020 1 次提交
  6. 26 12月, 2019 1 次提交
  7. 22 12月, 2019 2 次提交
  8. 20 12月, 2019 1 次提交
    • C
      riscv: move sifive_l2_cache.c to drivers/soc · 9209fb51
      Christoph Hellwig 提交于
      The sifive_l2_cache.c is in no way related to RISC-V architecture
      memory management.  It is a little stub driver working around the fact
      that the EDAC maintainers prefer their drivers to be structured in a
      certain way that doesn't fit the SiFive SOCs.
      
      Move the file to drivers/soc and add a Kconfig option for it, as well
      as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE.
      
      Fixes: a967a289 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
      Signed-off-by: NChristoph Hellwig <hch@lst.de>
      Reviewed-by: NBorislav Petkov <bp@suse.de>
      [paul.walmsley@sifive.com: keep the MAINTAINERS change specific to the L2$ controller code]
      Signed-off-by: NPaul Walmsley <paul.walmsley@sifive.com>
      9209fb51
  9. 14 12月, 2019 1 次提交
  10. 11 12月, 2019 1 次提交
  11. 10 12月, 2019 4 次提交
  12. 08 12月, 2019 2 次提交
  13. 07 12月, 2019 3 次提交
  14. 06 12月, 2019 2 次提交
  15. 03 12月, 2019 2 次提交
  16. 01 12月, 2019 1 次提交
  17. 27 11月, 2019 5 次提交
  18. 26 11月, 2019 2 次提交
  19. 25 11月, 2019 4 次提交
  20. 23 11月, 2019 2 次提交