TI_TASK is not used in nios2 assembly code, so remove it.
Signed-off-by: NTobias Klauser <tklauser@distanz.ch>
Acked-by: NLey Foon Tan <lftan@altera.com>

The irq member of struct nios2_timer is only written to but
never read, thus it can be removed.
Signed-off-by: NTobias Klauser <tklauser@distanz.ch>
Acked-by: NLey Foon Tan <lftan@altera.com>

shm_align_mask is not defined/used on nios2, thus there is no need to
declare it.
Signed-off-by: NTobias Klauser <tklauser@distanz.ch>
Acked-by: NLey Foon Tan <lftan@altera.com>

This is require for __iomem definition.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

Move asm-generic/io.h to end of file to override functions like
phys_to_virt, virt_to_phys in asm-generic/io.h.
This is due to recent commit 9216efaf introduced new way to
override functions by checking for the existence of a macro with the
same of the function.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

Don't need asm-generic/iomap.h and asm-generic/io.h added
default ioread8/16/32 iowrite8/16/32 implementation.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

Remove extra space between # and define.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

Return value of irq_of_parse_and_map() is unsigned int, with 0
indicating failure, so testing for negative result never works.
Signed-off-by: NDmitry Torokhov <dtor@chromium.org>
Reviewed-by: NTobias Klauser <tklauser@distanz.ch>
Acked-by: NLey Foon Tan <lftan@altera.com>

Make the checking for div/mul/mulx instruction config symbols easier to
read by using IS_ENABLED instead of #ifdefs.
Signed-off-by: NTobias Klauser <tklauser@distanz.ch>
Acked-by: NLey Foon Tan <lftan@altera.com>

This patch adds Makefile and Kconfig files required for building a
nios2 kernel.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

Add ptrace support for nios2.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This patch adds support for loadable modules.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This file contains constants for the instruction macros, cpu registers,
fields and bits.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This patch introduces a few nios2-specific header files.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

Signed-off-by: NLey Foon Tan <lftan@altera.com>

Add time keeping code for nios2.
Signed-off-by: NLey Foon Tan <lftan@altera.com>
Reviewed-by: NThomas Gleixner <tglx@linutronix.de>

Add device tree support to arch/nios2.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

Add optimised library functions for nios2.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This patch adds support for signal handling.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This patch adds support for system calls from userspaces. It uses the
asm-generic/unistd.h definitions with architecture spcific syscall.
The sys_call_table is just an array defined in a C file and it contains
pointers to the syscall functions.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This patch adds definitions for the ELF format
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This patch adds support for the DMA mapping API.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This patch adds the support for IRQ handling.
Signed-off-by: NLey Foon Tan <lftan@altera.com>
Reviewed-by: NThomas Gleixner <tglx@linutronix.de>

This patch adds the TLB maintenance functions.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This patch adds functionality required for cache maintenance.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This patch adds support for thread creation and context switching.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This patch adds support for page table management.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This patch adds support for the handling of the MMU faults (exception
entry code introduced by a previous patch, kernel/entry.S).
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This patch adds several definitions for I/O accessors and ioremap().
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This patch contains the initialisation of the memory blocks, MMU
attributes and the memory map.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This patch contains traps exception handling.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This patch contains the exception entry code (kernel/entry.S) and
misaligned exception.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This patch adds the kernel booting and the initial setup code.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

This patch add assembly macros and definitions used in
the .S files across arch/nios2/ and together with asm-offsets.c.
Signed-off-by: NLey Foon Tan <lftan@altera.com>

Commit eb7e7d76 "s390: Replace __get_cpu_var uses" broke machine check
handling.

We copy machine check information from per-cpu to a stack variable for
local processing. Next we should zap the per-cpu variable, not the
stack variable.
Signed-off-by: NSebastian Ott <sebott@linux.vnet.ibm.com>
Reviewed-by: NHeiko Carstens <heiko.carstens@de.ibm.com>
Acked-by: NChristoph Lameter <cl@linux.com>
Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>

First, there was this: https://bugzilla.kernel.org/show_bug.cgi?id=88001

The problem there was that microcode patches are not being reapplied
after suspend-to-ram. It was important to reapply them, though, because
of for example Haswell's TSX erratum which disabled TSX instructions
with a microcode patch.

A simple fix was fb86b973 ("x86, microcode: Update BSPs microcode
on resume") but, as it is often the case, simple fixes are too
simple. This one causes 32-bit resume to fail:

https://bugzilla.kernel.org/show_bug.cgi?id=88391

Properly fixing this would require more involved changes for which it
is too late now, right before the merge window. Thus, limit this to
64-bit only temporarily.
Signed-off-by: NBorislav Petkov <bp@suse.de>
Link: http://lkml.kernel.org/r/1417353999-32236-1-git-send-email-bp@alien8.deSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

There is a potential race when probing the TLB in TLBL/M/S exception
handlers for a matching entry. Between the time we hit a TLBL/S/M
exception and the time we get to execute the TLBP instruction, the
HTW may have replaced the TLB entry we are interested in hence the TLB
probe may fail. However, in the existing handlers, we never checked the
status of the TLBP (ie check the result in the C0/Index register). We
fix this by adding such a check when the core implements the HTW. If
we couldn't find a matching entry, we return back and try again.
Signed-off-by: NLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com>
Reviewed-by: NJames Hogan <james.hogan@imgtec.com>
Cc: <stable@vger.kernel.org> # v3.17+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8599/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

We cannot restart cacheflush safely if a process provides user-defined
signal handler and signal is pending. In this case -EINTR is returned
and it is expected that process re-invokes syscall. However, there are
a few problems with that:
 * looks like nobody bothers checking return value from cacheflush
 * but if it did, we don't provide the restart address for that, so the
   process has to use the same range again
 * ...and again, what might lead to looping forever

So, remove cacheflush restarting code and terminate cache flushing
as early as fatal signal is pending.

Cc: stable@vger.kernel.org # 3.12+
Reported-by: NChanho Min <chanho.min@lge.com>
Signed-off-by: NVladimir Murzin <vladimir.murzin@arm.com>
Acked-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Under extremely rare conditions, in an MPCore node consisting of at
least 3 CPUs, two CPUs trying to perform a STREX to data on the same
shared cache line can enter a livelock situation.

This patch enables the HW mechanism that overcomes the bug. This fixes
the incorrect setup of the STREX backoff delay bit due to a wrong
description in the specification.

Note that enabling the STREX backoff delay mechanism is done by
leaving the bit *cleared*, while the bit was currently being set by
the proc-v7.S code.

[Thomas: adapt to latest mainline, slightly reword the commit log, add
stable markers.]

Fixes: de490193 ("arm: mm: Add support for PJ4B cpu and init routines")

Cc: <stable@vger.kernel.org> # v3.8+
Signed-off-by: NNadav Haklai <nadavh@marvell.com>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The crazy gic_arch_extn thing that Tegra uses contains multiple
references to the irq field in struct irq_data, and uses this
to directly poke hardware register.

But irq is the *virtual* irq number, something that has nothing
to do with the actual HW irq (stored in the hwirq field). And once
we put the stacked domain code in action, the whole thing explodes,
as these two values are *very* different:

root@bacon-fat:~# cat /proc/interrupts
            CPU0       CPU1
 16:      25801       2075       GIC  29  twd
 17:          0          0       GIC  73  timer0
112:          0          0      GPIO  58  c8000600.sdhci cd
123:          0          0      GPIO  69  c8000200.sdhci cd
279:       1126          0       GIC 122  serial
281:          0          0       GIC  70  7000c000.i2c
282:          0          0       GIC 116  7000c400.i2c
283:          0          0       GIC 124  7000c500.i2c
284:        300          0       GIC  85  7000d000.i2c
[...]

Just replacing all instances of irq with hwirq fixes the issue.
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>