1. 26 5月, 2011 1 次提交
    • M
      x86, efi: Retain boot service code until after switching to virtual mode · 916f676f
      Matthew Garrett 提交于
      UEFI stands for "Unified Extensible Firmware Interface", where "Firmware"
      is an ancient African word meaning "Why do something right when you can
      do it so wrong that children will weep and brave adults will cower before
      you", and "UEI" is Celtic for "We missed DOS so we burned it into your
      ROMs". The UEFI specification provides for runtime services (ie, another
      way for the operating system to be forced to depend on the firmware) and
      we rely on these for certain trivial tasks such as setting up the
      bootloader. But some hardware fails to work if we attempt to use these
      runtime services from physical mode, and so we have to switch into virtual
      mode. So far so dreadful.
      
      The specification makes it clear that the operating system is free to do
      whatever it wants with boot services code after ExitBootServices() has been
      called. SetVirtualAddressMap() can't be called until ExitBootServices() has
      been. So, obviously, a whole bunch of EFI implementations call into boot
      services code when we do that. Since we've been charmingly naive and
      trusted that the specification may be somehow relevant to the real world,
      we've already stuffed a picture of a penguin or something in that address
      space. And just to make things more entertaining, we've also marked it
      non-executable.
      
      This patch allocates the boot services regions during EFI init and makes
      sure that they're executable. Then, after SetVirtualAddressMap(), it
      discards them and everyone lives happily ever after. Except for the ones
      who have to work on EFI, who live sad lives haunted by the knowledge that
      someone's eventually going to write yet another firmware specification.
      
      [ hpa: adding this to urgent with a stable tag since it fixes currently-broken
        hardware.  However, I do not know what the dependencies are and so I do
        not know which -stable versions this may be a candidate for. ]
      Signed-off-by: NMatthew Garrett <mjg@redhat.com>
      Link: http://lkml.kernel.org/r/1306331593-28715-1-git-send-email-mjg@redhat.comSigned-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: <stable@kernel.org>
      916f676f
  2. 25 5月, 2011 2 次提交
    • C
      x86, UV: Clean up uv_tlb.c · f073cc8f
      Cliff Wickman 提交于
      SGI UV's uv_tlb.c driver has become rather hard to read, with overly large
      functions, non-standard coding style and (way) too long variable, constant
      and function names and non-obvious code flow sequences.
      
      This patch improves the readability and maintainability of the driver
      significantly, by doing the following strict code cleanups with no side
      effects:
      
       - Split long functions into shorter logical functions.
      
       - Shortened some variable and structure member names.
      
       - Added special functions for reads and writes of MMR regs with
         very long names.
      
       - Added the 'tunables' table to shortened tunables_write().
      
       - Added the 'stat_description' table to shorten uv_ptc_proc_write().
      
       - Pass fewer 'stat' arguments where it can be derived from the 'bcp'
         argument.
      
       - Function definitions consistent on one line, and inline in few (short) cases.
      
       - Moved some small structures and an atomic inline function to the header file.
      
       - Moved some local variables to the blocks where they are used.
      
       - Updated the copyright date.
      
       - Shortened uv_write_global_mmr64() etc. using some aliasing; no
         line breaks. Renamed many uv_.. functions that are not exported.
      
       - Aligned structure fields.
          [ note that not all structures are aligned the same way though; I'd like
            to keep the extensive commenting in some of them. ]
      
       - Shortened some long structure names.
      
       - Standard pass/fail exit from init_per_cpu()
      
       - Vertical alignment for mass initializations.
      
       - More separation between blocks of code.
      
      Tested on a 16-processor Altix UV.
      Signed-off-by: NCliff Wickman <cpw@sgi.com>
      Cc: penberg@kernel.org
      Link: http://lkml.kernel.org/r/E1QOw12-0004MN-Lp@eag09.americas.sgi.comSigned-off-by: NIngo Molnar <mingo@elte.hu>
      f073cc8f
    • J
      x86, UV: Add support for SGI UV2 hub chip · 2a919596
      Jack Steiner 提交于
      This patch adds support for a new version of the SGI UV hub
      chip. The hub chip is the node controller that connects multiple
      blades into a larger coherent SSI.
      
      For the most part, UV2 is compatible with UV1. The majority of
      the changes are in the addresses of MMRs and in a few cases, the
      contents of MMRs. These changes are the result in changes in the
      system topology such as node configuration, processor types,
      maximum nodes, physical address sizes, etc.
      Signed-off-by: NJack Steiner <steiner@sgi.com>
      Link: http://lkml.kernel.org/r/20110511175028.GA18006@sgi.comSigned-off-by: NIngo Molnar <mingo@elte.hu>
      2a919596
  3. 13 5月, 2011 1 次提交
    • C
      x86: Fix UV BAU for non-consecutive nasids · 77ed23f8
      Cliff Wickman 提交于
      This is a fix for the SGI Altix-UV Broadcast Assist Unit code,
      which is used for TLB flushing.
      
      Certain hardware configurations (that customers are ordering)
      cause nasids (numa address space id's) to be non-consecutive.
      Specifically, once you have more than 4 blades in a IRU
      (Individual Rack Unit - or 1/2 rack) but less than the maximum
      of 16, the nasid numbering becomes non-consecutive.  This
      currently results in a 'catastrophic error' (CATERR) detected by
      the firmware during OS boot.  The BAU is generating an 'INTD'
      request that is targeting a non-existent nasid value. Such
      configurations may also occur when a blade is configured off
      because of hardware errors. (There is one UV hub per blade.)
      
      This patch is required to support such configurations.
      
      The problem with the tlb_uv.c code is that is using the
      consecutive hub numbers as indices to the BAU distribution bit
      map. These are simply the ordinal position of the hub or blade
      within its partition.  It should be using physical node numbers
      (pnodes), which correspond to the physical nasid values. Use of
      the hub number only works as long as the nasids in the partition
      are consecutive and increase with a stride of 1.
      
      This patch changes the index to be the pnode number, thus
      allowing nasids to be non-consecutive.
      It also provides a table in local memory for each cpu to
      translate target cpu number to target pnode and nasid.
      And it improves naming to properly reflect 'node' and 'uvhub'
      versus 'nasid'.
      Signed-off-by: NCliff Wickman <cpw@sgi.com>
      Cc: <stable@kernel.org>
      Link: http://lkml.kernel.org/r/E1QJmxX-0002Mz-Fk@eag09.americas.sgi.comSigned-off-by: NIngo Molnar <mingo@elte.hu>
      77ed23f8
  4. 10 5月, 2011 5 次提交
  5. 07 5月, 2011 1 次提交
  6. 28 4月, 2011 1 次提交
  7. 12 4月, 2011 1 次提交
    • J
      x86/mrst: Fix boot crash caused by incorrect pin to irq mapping · 9d90e49d
      Jacob Pan 提交于
      Moorestown systems crash on boot because the secondary CPU
      clockevent (apbt1) will fail to request irq#1, which does not
      have ioapic chip in its irq_desc[] entry.
      
      Background:
      
      Moorestown platform does not have ISA bus nor legacy IRQs. It
      reuses the range of legacy IRQs for regular device interrupts.
      The routing information of early system device IRQs (timers) are
      obtained from firmware provided SFI tables. We reuse/fake MP
      configuration table to facilitate IRQ setup with IOAPIC.
      
      Maintaining a 1:1 mapping of IOAPIC pin (RTE entry) and IRQ#
      makes routing information clean and easy to understand on
      Moorestown. Though optional.
      
      This patch allows SFI timer and vRTC IRQ to be treated as ISA
      IRQ so that pin2irq mapping will be 1:1.
      
      Also fixed MP table type and use macros to clearly set MP IRQ
      entries. As a result, apbt timer and RTC interrupts on
      Moorestown are within legacy IRQ range:
      
       # cat /proc/interrupts
                  CPU0       CPU1
         0:      11249          0   IO-APIC-edge      apbt0
         1:          0      12271   IO-APIC-edge      apbt1
         8:        887          0   IO-APIC-fasteoi   dw_spi
        13:          0          0   IO-APIC-fasteoi   INTEL_MID_DMAC2
        14:          0          0   IO-APIC-fasteoi   rtc0
      
      Further discussion of this patch can be found at:
      
        https://lkml.org/lkml/2010/6/10/70Suggested-by: N"Eric W. Biederman" <ebiederm@xmission.com>
      Signed-off-by: NJacob Pan <jacob.jun.pan@linux.intel.com>
      Cc: Feng Tang <feng.tang@intel.com>
      Cc: Alan Cox <alan@linux.intel.com>
      Cc: Arjan van de Ven <arjan@linux.intel.com>
      Link: http://lkml.kernel.org/r/1302286980-21139-1-git-send-email-jacob.jun.pan@linux.intel.comSigned-off-by: NIngo Molnar <mingo@elte.hu>
      9d90e49d
  8. 11 4月, 2011 1 次提交
  9. 07 4月, 2011 1 次提交
  10. 04 4月, 2011 1 次提交
  11. 29 3月, 2011 1 次提交
    • J
      x86: Stop including <linux/delay.h> in two asm header files · ca444564
      Jean Delvare 提交于
      Stop including <linux/delay.h> in x86 header files which don't
      need it. This will let the compiler complain when this header is
      not included by source files when it should, so that
      contributors can fix the problem before building on other
      architectures starts to fail.
      
      Credits go to Geert for the idea.
      Signed-off-by: NJean Delvare <khali@linux-fr.org>
      Cc: James E.J. Bottomley <James.Bottomley@suse.de>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Cc: Stephen Rothwell <sfr@canb.auug.org.au>
      LKML-Reference: <20110325152014.297890ec@endymion.delvare>
      [ this also fixes an upstream build bug in drivers/media/rc/ite-cir.c ]
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      ca444564
  12. 27 3月, 2011 2 次提交
  13. 23 3月, 2011 2 次提交
  14. 16 3月, 2011 1 次提交
  15. 14 3月, 2011 1 次提交
  16. 12 3月, 2011 2 次提交
  17. 09 3月, 2011 1 次提交
  18. 03 3月, 2011 1 次提交
  19. 25 2月, 2011 1 次提交
    • T
      x86: dt: Cleanup local apic setup · a906fdaa
      Thomas Gleixner 提交于
      Up to now we force enable the local apic in the devicetree setup
      uncoditionally and set smp_found_config unconditionally to 1 when a
      devicetree blob is available. This breaks, when local apic is disabled
      in the Kconfig.
      
      Make it consistent by initializing device tree explicitely before
      smp_get_config() so a non lapic configuration could be used as well.
      To be functional that would require to implement PIT as an interrupt
      host, but the only user of this code until now is ce4100 which
      requires apics to be available. So we leave this up to those who need
      it.
      Tested-by: NSebastian Siewior <bigeasy@linutronix.de>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      a906fdaa
  20. 24 2月, 2011 2 次提交
    • S
      x86: ce4100: Use OF to setup devices · 1fa4163b
      Sebastian Andrzej Siewior 提交于
      Use device tree information to setup IO_APIC configuration, interrupt
      routing, HPET and everything else which cannot be enumerated by other
      means.
      Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
      Signed-off-by: NDirk Brandewie <dirk.brandewie@gmail.com>
      Acked-by: NGrant Likely <grant.likely@secretlab.ca>
      Cc: sodaville@linutronix.de
      Cc: devicetree-discuss@lists.ozlabs.org
      LKML-Reference: <1298405266-1624-11-git-send-email-bigeasy@linutronix.de>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      1fa4163b
    • S
      x86: dtb: Add a device tree for CE4100 · df2634f4
      Sebastian Andrzej Siewior 提交于
      History:
      v1..v2:
      - dropped device_type except for cpu & pci. I have the compatible string
        for pci so I can drop the device_type once it is possible
      - I lowercased all compatible types. I will need to resend some patches
        which have upper case intel
      - The cpu had the same compatible string as the soc node. So I added to
        the soc node -immr for internel memory mapped registers.
      - I added generic names for all parts.
      - I reworked the i2c bars matching the way you suggested. I added a
        compatible node for the PCI device which only the PCI ids in its
        compatible string. The bars (each represents a complete i2c
        controller) have a "intel,ce4100-i2c-controller" compatible node. It
        is not used by the driver.
        The driver is probed via PCI ids (by the pci subsystem not OF) and
        matches the bar address against the ressource in the child node. Once
        there is a hit the node is attached.
      - The SPI driver is also probed via pci. However I also attached a
        compatible property based on PCI ids
      
      v2..v3:
      - intel,ce4100-immr become intel,ce4100-cp. cp stands for core
        peripherals. The Atom data sheet talks here about ACPI devices. Since
        we don't have ACPI this does not apply here.
      - The interrupt map is gone. There are now plenty of device nodes.
      - The "unit address string" got fixed, it uses not DD,V format.
      
      v3..v4:
      - added descriptions for compatible nodes introduced here:
        - intel,ce4100-ioapic
        - intel,ce4100-lapic
        - intel,ce4100-hpet
        - intel,ce4100
        - intel,ce4100-cp
        - intel,ce4100-pci
      - added a description about I2C controller magic.
      - Added gpio-controller and gpio-cells property to gpio devices. Those
        properties are not (yet) used.
      Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
      Signed-off-by: NDirk Brandewie <dirk.brandewie@gmail.com>
      Acked-by: NGrant Likely <grant.likely@secretlab.ca>
      Cc: sodaville@linutronix.de
      Cc: devicetree-discuss@lists.ozlabs.org
      LKML-Reference: <1298405266-1624-4-git-send-email-bigeasy@linutronix.de>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      df2634f4
  21. 23 2月, 2011 2 次提交
  22. 22 2月, 2011 1 次提交
    • J
      x86: Convert remaining x86 clocksources to clocksource_register_hz/khz · b01cc1b0
      John Stultz 提交于
      This converts the remaining x86 clocksources to use
      clocksource_register_hz/khz.
      
      CC: jacob.jun.pan@intel.com
      CC: Glauber Costa <glommer@redhat.com>
      CC: Dimitri Sivanich <sivanich@sgi.com>
      CC: Rusty Russell <rusty@rustcorp.com.au>
      CC: Jeremy Fitzhardinge <jeremy@xensource.com>
      CC: Chris McDermott <lcm@us.ibm.com>
      CC: Thomas Gleixner <tglx@linutronix.de>
      Tested-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> [xen]
      Signed-off-by: NJohn Stultz <johnstul@us.ibm.com>
      b01cc1b0
  23. 15 2月, 2011 1 次提交
  24. 14 1月, 2011 1 次提交
  25. 05 1月, 2011 1 次提交
    • Y
      x86: Fix APIC ID sizing bug on larger systems, clean up MAX_APICS confusion · cb2ded37
      Yinghai Lu 提交于
      Found one x2apic pre-enabled system, x2apic_mode suddenly get
      corrupted after register some cpus, when compiled
      CONFIG_NR_CPUS=255 instead of 512.
      
      It turns out that generic_processor_info() ==> phyid_set(apicid,
      phys_cpu_present_map) causes the problem.
      
      phys_cpu_present_map is sized by MAX_APICS bits, and pre-enabled
      system some cpus have an apic id > 255.
      
      The variable after phys_cpu_present_map may get corrupted
      silently:
      
       ffffffff828e8420 B phys_cpu_present_map
       ffffffff828e8440 B apic_verbosity
       ffffffff828e8444 B local_apic_timer_c2_ok
       ffffffff828e8448 B disable_apic
       ffffffff828e844c B x2apic_mode
       ffffffff828e8450 B x2apic_disabled
       ffffffff828e8454 B num_processors
       ...
      
      Actually phys_cpu_present_map is referenced via apic id, instead
      index. We should use MAX_LOCAL_APIC instead MAX_APICS.
      
      For 64-bit it will be 32768 in all cases. BSS will increase by 4k bytes
      on 64-bit:
      
      	text		data		bss		dec		filename
      	21696943	4193748		12787712	38678403	vmlinux.before
      	21696943	4193748		12791808	38682499	vmlinux.after
      
      No change on 32bit.
      
      Finally we can remove MAX_APCIS that was rather confusing.
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Cc: H. Peter Anvin <hpa@linux.intel.com>
      Cc: "Eric W. Biederman" <ebiederm@xmission.com>
      LKML-Reference: <4D23BD9C.3070102@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      cb2ded37
  26. 04 1月, 2011 1 次提交
    • C
      x86, UV, BAU: Extend for more than 16 cpus per socket · cfa60917
      Cliff Wickman 提交于
      Fix a hard-coded limit of a maximum of 16 cpu's per socket.
      
      The UV Broadcast Assist Unit code initializes by scanning the
      cpu topology of the system and assigning a master cpu for each
      socket and UV hub. That scan had an assumption of a limit of 16
      cpus per socket. With Westmere we are going over that limit.
      The UV hub hardware will allow up to 32.
      
      If the scan finds the system has gone over that limit it returns
      an error and we print a warning and fall back to doing TLB
      shootdowns without the BAU.
      Signed-off-by: NCliff Wickman <cpw@sgi.com>
      Cc: <stable@kernel.org> # .37.x
      LKML-Reference: <E1PZol7-0000mM-77@eag09.americas.sgi.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      cfa60917
  27. 16 12月, 2010 2 次提交
    • A
      x86, olpc: Speed up device tree creation during boot · b5318d30
      Andres Salomon 提交于
      Calling alloc_bootmem() for tiny chunks of memory over and over is really
      slow; on an XO-1, it caused the time between when the kernel started
      booting and when the display came alive (post-lxfb probe) to increase
      to 44s.  This patch optimizes the prom_early_alloc function by
      calling alloc_bootmem for 4k-sized blocks of memory, and handing out
      chunks of that to callers.  With this patch, the time between kernel load
      and display initialization decreased to 23s.  If there's a better way to
      do this early in the boot process, please let me know.
      
      (Note: increasing the chunk size to 16k didn't noticably affect boot time,
      and wasted 9k.)
      
      v4: clarify comment, requested by hpa
      v3: fix wasted memory buglet found by Milton Miller, and style fix.
      v2: reorder prom_early_alloc as suggested by Grant.
      Signed-off-by: NAndres Salomon <dilinger@queued.net>
      LKML-Reference: <20101129153951.74202a84@queued.net>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      b5318d30
    • A
      x86, olpc: Add OLPC device-tree support · c10d1e26
      Andres Salomon 提交于
      Make use of PROC_DEVICETREE to export the tree, and sparc's PROMTREE code to
      call into OLPC's Open Firmware to build the tree.
      
      v5: fix buglet with root node check (introduced in v4)
      
      v4: address some minor style issues pointed out by Grant, and explicitly cast
          negative phandle checks to s32.
      
      v3: rename olpc_prom to olpc_dt
        - rework Kconfig entries
        - drop devtree build hook from proc, instead adding a call to x86's
          paging_init (similarly to how sparc64 does it)
        - switch allocation from using slab to alloc_bootmem.  this allows
          the DT to be built earlier during boot (during setup_arch); the
          downside is that there are some 1200 bootmem reservations that are
          done during boot.  Not ideal..
        - add a helper olpc_ofw_is_installed function to test for the
          existence and successful detection of OLPC's OFW.
      Signed-off-by: NAndres Salomon <dilinger@queued.net>
      LKML-Reference: <20101116220952.26526a80@queued.net>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      c10d1e26
  28. 10 12月, 2010 2 次提交