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  1. 27 11月, 2013 17 次提交
  3. 26 11月, 2013 9 次提交
    • S
      ARM: bcm2835: add missing #xxx-cells to I2C nodes · a31ab44e
      由 Stephen Warren 提交于 
      The I2C controller node needs #address-cells and #size-cells properties,
but these are currently missing. Add them. This allows child nodes to be
parsed correctly.

Cc: stable@vger.kernel.org
Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>
      a31ab44e
    • D
      ARM: dts: Add max77686 RTC interrupt to cros5250-common · c61248af
      由 Doug Anderson 提交于 
      Without the interrupt you'll get problems if you enable
CONFIG_RTC_DRV_MAX77686.  Setup the interrupt properly in the device
tree.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>
Cc: stable@vger.kernel.org
      c61248af
    • T
      ARM: OMAP2+: Fix eMMC on n900 with device tree · edd5eb4e
      由 Tony Lindgren 提交于 
      Looks like we need to configure the regulators and use the pdata
quirk to make eMMC work with device tree.

It seems that mostly vaux3 is used, and only some earlier revisions
used vmmc2. This has been tested to work on devices where the
system_rev passed by the bootloader has versions 0x0010, 0x2101
and 0x2204.

Cc: devicetree@vger.kernel.org
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: NSebastian Reichel <sre@debian.org>
[tony@atomide.com: updated with pinctrl changes and comments from Sebastian]
Signed-off-by: NTony Lindgren <tony@atomide.com>
      edd5eb4e
    • T
      ARM: OMAP2+: Add fixed regulator to omap2plus_defconfig · 26f67a31
      由 Tony Lindgren 提交于 
      We do not have REGULATOR_FIXED selected if no boards are selected
and we boot with device tree. This can cause various devices to
fail.
Signed-off-by: NTony Lindgren <tony@atomide.com>
      26f67a31
    • T
      ARM: OMAP2+: Fix more missing data for omap3.dtsi file · 7ce93f31
      由 Tony Lindgren 提交于 
      After dropping the duplicate data in hwmod that now should come from
the .dts files, I noticed few more entries missing. Let's add these
as otherwise devices relying on these won't work.

Looks like the side tone entries are bundled into the mcbsp1 to 3,
so that may needs some special handling in the hwmod code as it's
currently trying to look up mcbsp2_sidetone and mcbsp3_sidetone
entries.
Signed-off-by: NTony Lindgren <tony@atomide.com>
      7ce93f31
    • D
      ARM: vexpress/TC2: Implement MCPM power_down_finish() · 33cb667a
      由 Dave Martin 提交于 
      This patch implements the power_down_finish() method for TC2, to
enable the kernel to confirm when CPUs are safely powered down.

The information required for determining when a CPU is parked
cannot be obtained from any single place, so a few sources of
information must be combined:

  * mcpm_cpu_power_down() must be pending for the CPU, so that we
    don't get confused by false STANDBYWFI positives arising from
    CPUidle.  This is detected by waiting for the tc2_pm use count
    for the target CPU to reach 0.

  * Either the SPC must report that the CPU has asserted
    STANDBYWFI, or the TC2 tile's reset control logic must be
    holding the CPU in reset.

    Just checking for STANDBYWFI is not sufficient, because this
    signal is not latched when the the cluster is clamped off and
    powered down: the relevant status bits just drop to zero.  This
    means that STANDBYWFI status cannot be used for reliable
    detection of the last CPU in a cluster reaching WFI.

This patch is required in order for kexec to work with MCPM on TC2.

MCPM code was changed in commit 0de0d646 ('ARM: 7848/1: mcpm:
Implement cpu_kill() to synchronise on powerdown'), and since then it
will hit a WARN_ON_ONCE() due to power_down_finish not being implemented
on the TC2 platform.
Signed-off-by: NDave Martin <Dave.Martin@arm.com>
Acked-by: NPawel Moll <pawel.moll@arm.com>
Reviewed-by: NNicolas Pitre <nico@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>
      33cb667a
    • O
      ARM: omap: fix warning with LPAE build · 6dd1e357
      由 Olof Johansson 提交于 
      Some omap3 code is throwing a warning:
arch/arm/mach-omap2/pm34xx.c: In function 'omap3_save_secure_ram_context':
arch/arm/mach-omap2/pm34xx.c:123:32: warning: cast to pointer from
  integer of different size [-Wint-to-pointer-cast]

In reality this code will never actually execute with LPAE=y, since
Cortex-A8 doesn't support it. So downcasting the __pa() is safe in
this case.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Acked-by: NTony Lindgren <tony@atomide.com>
      6dd1e357
    • T
      ARM: mvebu: re-enable PCIe on Armada 370 DB · 96039f73
      由 Thomas Petazzoni 提交于 
      Commit 14fd8ed0 ("ARM: mvebu: Relocate Armada 370/XP PCIe
device tree nodes") relocated the PCIe controller DT nodes one level
up in the Device Tree, to reflect a more correct representation of the
hardware introduced by the mvebu-mbus Device Tree binding.

However, while most of the boards were properly adjusted accordingly,
the Armada 370 DB board was left unchanged, and therefore, PCIe is
seen as not enabled on this board. This patch fixes that by moving the
PCIe controller node one level-up in armada-370-db.dts.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.12+
Fixes: 14fd8ed0 "ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes"
Signed-off-by: NJason Cooper <jason@lakedaemon.net>
      96039f73
    • G
      ARM: mvebu: use the virtual CPU registers to access coherency registers · b6dda00c
      由 Gregory CLEMENT 提交于 
      The Armada XP provides a mechanism called "virtual CPU registers" or
"per-CPU register banking", to access the per-CPU registers of the
current CPU, without having to worry about finding on which CPU we're
running. CPU0 has its registers at 0x21800, CPU1 at 0x21900, CPU2 at
0x21A00 and CPU3 at 0x21B00. The virtual registers accessing the
current CPU registers are at 0x21000.

However, in the Device Tree node that provides the register addresses
for the coherency unit (which is responsible for ensuring coherency
between processors, and I/O coherency between processors and the
DMA-capable devices), a mistake was made: the CPU0-specific registers
were specified instead of the virtual CPU registers. This means that
the coherency barrier needed for I/O coherency was not behaving
properly when executed from a CPU different from CPU0. This patch
fixes that by using the virtual CPU registers.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.8+
Fixes: e60304f8 "arm: mvebu: Add hardware I/O Coherency support"
Signed-off-by: NJason Cooper <jason@lakedaemon.net>
      b6dda00c
  5. 23 11月, 2013 2 次提交
  7. 21 11月, 2013 2 次提交
  9. 19 11月, 2013 5 次提交
  11. 18 11月, 2013 2 次提交
  13. 17 11月, 2013 1 次提交
  15. 16 11月, 2013 2 次提交
    • T
      ARM: dts: Fix omap2 specific dtsi files by adding the missing entries · 467f4bd2
      由 Tony Lindgren 提交于 
      Looks like we're missing few entries for omap2 and the drivers
have only worked because of the omap hwmod building the devices
for the missing entries.

Let's fix the missing entries so we don't need to rely on hwmod
for the basic data and can then later on remove the duplicate
data from hwmod. Otherwise device tree only drivers will not
work properly.

Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: NTony Lindgren <tony@atomide.com>
      467f4bd2
    • T
      ARM: OMAP2+: Fix GPMC and simplify bootloader timings for 8250 and smc91x · fd4446f2
      由 Tony Lindgren 提交于 
      Commit f2bf0e72 (ARM: OMAP2+: Add minimal 8250 support
for GPMC) added support for using bootloader timings for some
devices. Turns out we can do the same by looking at the compatible
flags of the child without adding a new function as smc91x has
a similar issue as 8250 with the bootloader timings.

And let's fix the 8250 naming, we should use the device type as
the name like uart instead of 8250 for zoom dts file.

Cc: "Benoît Cousson" <bcousson@baylibre.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
      fd4446f2