This patch adds node for GMAC for exynos5440 SoC supported by GMAC
driver.
Signed-off-by: NByungho An <bh74.an@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Exynos5440 pin-controller generates eight interrupts to support
gpio interrupts. List those interrupt numbers in the pin-controller
node.
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add DT binding documentation for the FIMD IP block found in Samsung SoCs.
Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds FIMD related nodes for the Origen Quad board.
Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds a common FIMD device node for all Exynos4 SoCs.
Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds device tree node for the SYSREG registers block
found in Samsung S5P/Exynos SoC series. The SYSREG module
generates control signals for the ARM CPU and various IP blocks
and buses. SYSREG block registers are exposed through APB bus
interface. A sysreg device tree node is to be associated with
mfd syscon driver and all SYSREG clients should use regmap
interface it provides. It allows to eliminate any possible races
and conflicts should different drivers attempt to concurrently
access same register.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add display timing node to exynos5250-smdk5250.dts
Signed-off-by: NLeela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This adds common FIMD device node for all Exynos5 SoCs
Signed-off-by: NLeela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Exynos5440 has GIC which has virtualization support
in them. These are used by KVM.
Signed-off-by: NGiridhar Maruthy <giridhar.m@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The exynox4210-ehci and exynos4210-ohci nodes need a clock specified
using the common clock framework.  Document it.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This is a fixup to two device tree nodes that have already landed but
without clock nodes since the transition to common clock happened at
the same time.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Reviewed-by: NJingoo Han <jg1.han@samsung.com>
[gautam.vivek@samsung.com: tested on smdk5250]
Tested-by: NVivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The exynos 5250 SoC supports A15 style architected timers. Indicate
this through the device tree.

This is required by KVM.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The GIC in the exynos5250 SoC is A15 compliant. Show this through
the device tree, so that we can use the GIC for KVM.

Also add the respective A15 memory regions and interrupt links.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Added HDMI hot plug and regulator nodes to Arndale DT file.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NTushar Behera <tushar.behera@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Added MFC codec node to Arndale DT file.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Added vmmc regulator node to Arndale DT file.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NTushar Behera <tushar.behera@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Added S5M8767 PMIC DT nodes for Arndale board. Only the used
LDO's/BUCK are defined here. Also the nodes describe the default/reset
state LDO's and no power mangement tuning is implemented. The usage
desription can be found in s5m8767 device tree binding documentation.
Signed-off-by: NAmit Daniel Kachhap <amit.daniel@samsung.com>
Signed-off-by: NTushar Behera <tushar.behera@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Added GPIO buttons DT node to Arndale board file.
Signed-off-by: NTushar Behera <tushar.behera@linaro.org>
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This is required to keep the existing functionality of having no
write protect pin on Arndale board.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NTushar Behera <tushar.behera@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Signed-off-by: NTushar Behera <tushar.behera@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add default pin state information for all client nodes that require
pin configuration support using pinctrl interface.
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add default pin state information for all client nodes that require
pin configuration support using pinctrl interface.
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Added documentaion about G2D bindings.

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Inki Dae <inki.dae@samsung.com>
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Added G2D DT node to Origen4412 board.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Added G2D DT node to SMDK4412 board.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Added G2D DT node to exynos4x12.dtsi file.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Added G2D DT node to Origen4210 board.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Added G2D DT node to SMDKV310 board.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Added G2D DT node to Exynos4210.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Conflicts:
	arch/arm/boot/dts/exynos4.dtsi
	arch/arm/boot/dts/exynos5440.dtsi

The functions exynos4_clk_init and exynos4_clk_register_fixed_ext
are applicable only on Exynos4 non-dt platforms. But when building
Exynos5 platforms without including Exynos4 platforms, the following
errors show up.

arch/arm/mach-exynos/built-in.o: In function `exynos_init_time':
arch/arm/mach-exynos/common.c:446: undefined reference to `exynos4_clk_init'
arch/arm/mach-exynos/common.c:447: undefined reference to `exynos4_clk_register_fixed_ext'

Fix this compilation errors by marking these calls as Exynos4 specific.
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide)
instead of RATIO bit-field (4-bit wide) for dividing clock rate.

With current common clock setup, we are using RATIO bit-field which
is creating FIFO read errors while accessing eMMC. Changing over to
use PRE_RATIO bit-field fixes this issue.

dwmmc_exynos 12200000.dwmmc0: data FIFO error (status=00008020)
mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0
end_request: I/O error, dev mmcblk0, sector 1
Signed-off-by: NTushar Behera <tushar.behera@linaro.org>
CC: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds clock indexes for ACLK_DIV0, ACLK_DIV1,
ACLK_400_MCUISP, ACLK_MCUISP_DIV0, ACLK_MCUISP_DIV1,
DIVACLK_400_MCUISP and DIVACLK_200 so these clocks are
available to the consumers (Exynos4x12 FIMC-IS subsystem).
While at it, indentation of the mux clocks table is
corrected.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Fixes the below compilation error during non-dt build.
drivers/clk/samsung/clk.c: In function 'samsung_clk_of_register_fixed_ext':
drivers/clk/samsung/clk.c:252:2: error: implicit declaration of function 'for_each_matching_node_and_match' [-Werror=implicit-function-declaration]
drivers/clk/samsung/clk.c:252:60: error: expected ';' before '{' token
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add gate clocks for fimd, mie, dsim, dp, mixer and hdmi.
Register it to common clock framework.
Signed-off-by: NLeela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch extends suspend/resume support for SoC-specific registers to
handle differences in register sets on particular SoCs.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NThomas Abraham <thomas.abraham@linaro.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds missing clock control registers to the list of registers
that should be saved across system suspend.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NThomas Abraham <thomas.abraham@linaro.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This register is present on all Exynos4 SoCs and so the prefix is
misleading.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NThomas Abraham <thomas.abraham@linaro.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This definition is specific for Exynos4210 (which has another location
than the same register on Exynos4x12 SoCs) and so needs appropriate
prefix.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NThomas Abraham <thomas.abraham@linaro.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds E4210 prefix to all registers related to LCD1 clock
domain, because they are present only on Exynos4210.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NThomas Abraham <thomas.abraham@linaro.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>