- 14 12月, 2017 6 次提交
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由 Masahiro Yamada 提交于
struct nand_buffers is malloc'ed in nand_scan_tail() just for containing three pointers. Squash this struct into nand_chip. Move and rename as follows: chip->buffers->ecccalc -> chip->ecc.calc_buf chip->buffers->ecccode -> chip->ecc.code_buf chip->buffers->databuf -> chip->data_buf Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Masahiro Yamada 提交于
The last/only user of NAND_OWN_BUFFERS (cafe_nand.c) has been reworked. This flag is no longer needed. Suggested-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Masahiro Yamada 提交于
This driver is the last/only user of NAND_OWN_BUFFERS. Boris suggested to remove this flag. Taking a closer look at this driver, it calls dma_alloc_coherent() for the concatenated area for the DMA bounce buffer + struct nand_buffers, but the latter does not need to be DMA-coherent; cafe_{write,read}_buf simply do memcpy() between buffers when usedma==1. Let's do dma_alloc_coherent() for the DMA bounce buffer in the front, and leave the nand_buffers allocation to nand_scan_tail(), then rip off NAND_OWN_BUFFERS. The magic number, 2112, is still mysterious (hard-coded writesize + oobsize ?), but this is not our main interest. I am keeping it. Suggested-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Miquel Raynal 提交于
Right now, the chip->data_interface field is populated in nand_scan_tail(), so after the whole NAND detection has taken place. This is fine because these timings are not yet used by the core so early in the probe process, but the situation is about to change with the introduction of ->exec_op(). Also, by convention, nand_scan_ident() is not supposed to allocate resources, only nand_scan_tail() can, so this prevent us from allocating and initializing the data_interface object in nand_scan_ident(). In order to solve this problem, directly embed a data_interface object in nand_chip so that we don't have to allocate it, and initialize it to ONFI SDR mode 0 at the very beginning of nand_scan_ident(). Signed-off-by: NMiquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Boris Brezillon 提交于
The core currently send the READ0 and SEQIN+PAGEPROG commands in nand_do_read/write_ops(). This is inconsistent with ->read/write_oob[_raw]() hooks behavior which are expected to send these commands. There's already a flag (NAND_ECC_CUSTOM_PAGE_ACCESS) to inform the core that a specific controller wants to send the READ/SEQIN+PAGEPROG commands on its own, but it's an opt-in flag, and existing drivers are unlikely to be updated to pass it. Moreover, some controllers cannot dissociate the READ/PAGEPROG commands from the associated data transfer and ECC engine activation, and developers have to hack things in their ->cmdfunc() implementation to handle such complex cases, or have to accept the perf penalty of sending twice the same command. To address this problem we are planning on adding a new interface which is passed all information about a NAND operation (including the amount of data to transfer) and replacing all calls to ->cmdfunc() to calls to this new ->exec_op() hook. But, in order to do that, we need to have all ->cmdfunc() calls placed near their associated ->read/write_buf/byte() calls. Modify the core and relevant drivers to make NAND_ECC_CUSTOM_PAGE_ACCESS the default case, and remove this flag. Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> [miquel.raynal@free-electrons.com: tested, fixed and rebased on nand/next] Signed-off-by: NMiquel Raynal <miquel.raynal@free-electrons.com> Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Boris Brezillon 提交于
This is part of the process of removing direct calls to ->cmdfunc() outside of the core in order to introduce a better interface to execute NAND operations. Here we provide several helpers and make use of them to remove all direct calls to ->cmdfunc(). This way, we can easily modify those helpers to make use of the new ->exec_op() interface when available. Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> [miquel.raynal@free-electrons.com: rebased and fixed some conflicts] Signed-off-by: NMiquel Raynal <miquel.raynal@free-electrons.com> Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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- 01 12月, 2017 6 次提交
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由 Miquel Raynal 提交于
Avoid using specific defined values for checking returned status of the ->erase() hook. Instead, use usual negative error values on failure, zero otherwise. Signed-off-by: NMiquel Raynal <miquel.raynal@free-electrons.com> Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Masahiro Yamada 提交于
The "dma_buf" is not used for a DMA bounce buffer, but for arranging the transferred data for the syndrome page layout. In fact, it is used in the PIO mode as well, so "dma_buf" is a misleading name. Rename it to "tmp_buf". Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Masahiro Yamada 提交于
'extern' is not necessary for function declarations. scripts/checkpatch.pl with --strict option reports the following: CHECK: extern prototypes should be avoided in .h files Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Jagdish Gediya 提交于
Bufnum mask is used to calculate page position in the internal SRAM. As IFC version 2.0.0 has 16KB of internal SRAM as compared to older versions which had 8KB. Hence bufnum mask needs to be updated. Signed-off-by: NJagdish Gediya <jagdish.gediya@nxp.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Jesse Chan 提交于
This change resolves a new compile-time warning when built as a loadable module: WARNING: modpost: missing MODULE_LICENSE() in drivers/mtd/nand/denali_pci.o see include/linux/module.h for more information This adds the license as "GPL v2", which matches the header of the file. MODULE_DESCRIPTION and MODULE_AUTHOR are also added. Signed-off-by: NJesse Chan <jc@linux.com> Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Sascha Hauer 提交于
The GPMI nand Kconfig help texts mentions that the GPMI nand driver might conflict with SD cards. The only conflict there might really be is that both controllers use the same pins, but this is resolved by the pincontroller setup in the device tree. In any way the GPMI driver can safely be enabled, the text is just wrong. Remove it. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com> Acked-by: NHan Xu <han.xu@nxp.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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- 30 11月, 2017 4 次提交
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由 Boris Brezillon 提交于
Setting read-retry parameters has no impact on the R/B pin, so waiting for the chip to be ready is useless. Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Miquel Raynal 提交于
Some drivers (like nand_hynix.c) call ->cmdfunc() with NAND_CMD_NONE and a column address and expect the controller to only send address cycles. Right now, the default ->cmdfunc() implementations provided by the core do not filter out the command cycle in this case and forwards the request to the controller driver through the ->cmd_ctrl() method. The thing is, NAND controller drivers can get this wrong and send a command cycle with a NAND_CMD_NONE opcode and since NAND_CMD_NONE is -1, and the command field is usually casted to an u8, we end up sending the 0xFF command which is actually a RESET operation. Add conditions in nand_command[_lp]() functions to sending the initial command cycle when command == NAND_CMD_NONE. Signed-off-by: NMiquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Gustavo A. R. Silva 提交于
Make use of the swap macro and remove unnecessary variables swap. This makes the code easier to read and maintain. This code was detected with the help of Coccinelle. Signed-off-by: NGustavo A. R. Silva <garsilva@embeddedor.com> Acked-by: NHan Xu <han.xu@nxp.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Xiaolei Li 提交于
Previously, we only select chips and then send reset command to a NAND device during resuming nand driver. There is a lack of deselecting chips. It is advised to reset and initialize a NAND device using nand_reset(). Signed-off-by: NXiaolei Li <xiaolei.li@mediatek.com> Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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- 14 11月, 2017 1 次提交
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由 Boris Brezillon 提交于
Commit e8e3edb9 ("mtd: create per-device and module-scope debugfs entries") tried to make MTD related debugfs stuff consistent across the MTD framework by creating a root <debugfs>/mtd/ directory containing one directory per MTD device. The problem is that, by default, the MTD layer only registers the master device if no partitions are defined for this master. This behavior breaks all drivers that expect mtd->dbg.dfs_dir to be filled correctly after calling mtd_device_register() in order to add their own debugfs entries. The only way we can force all MTD masters to be registered no matter if they expose partitions or not is by enabling the CONFIG_MTD_PARTITIONED_MASTER option. In such situations, there's no other solution but to accept skipping debugfs initialization when dbg.dfs_dir is invalid, and when this happens, inform the user that he should consider enabling CONFIG_MTD_PARTITIONED_MASTER. Fixes: e8e3edb9 ("mtd: create per-device and module-scope debugfs entries") Cc: <stable@vger.kernel.org> Cc: Mario J. Rugiero <mrugiero@gmail.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Reported-by: NRichard Weinberger <richard@nod.at> Signed-off-by: NRichard Weinberger <richard@nod.at>
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- 07 11月, 2017 1 次提交
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由 Arvind Yadav 提交于
mtd_partition are not supposed to change at runtime. Functions 'mtd_device_parse_register' working with const mtd_partition provided by <linux/mtd/mtd.h>. So mark the non-const structs as const. Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: NRichard Weinberger <richard@nod.at>
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- 02 11月, 2017 1 次提交
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由 Greg Kroah-Hartman 提交于
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: NKate Stewart <kstewart@linuxfoundation.org> Reviewed-by: NPhilippe Ombredanne <pombredanne@nexb.com> Reviewed-by: NThomas Gleixner <tglx@linutronix.de> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 31 10月, 2017 1 次提交
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由 Brent Taylor 提交于
When mtdoops calls mtd_panic_write(), it eventually calls panic_nand_write() in nand_base.c. In order to properly wait for the nand chip to be ready in panic_nand_wait(), the chip must first be selected. When using the atmel nand flash controller, a panic would occur due to a NULL pointer exception. Fixes: 2af7c653 ("mtd: Add panic_write for NAND flashes") Cc: <stable@vger.kernel.org> Signed-off-by: NBrent Taylor <motobud@gmail.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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- 30 10月, 2017 2 次提交
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由 Xiaolei Li 提交于
For MT2701 NAND Controller, there may generate infinite ECC decode IRQ during long time burn test on some platforms. Once this issue occurred, the ECC decode IRQ status cannot be cleared in the IRQ handler function, and threads cannot be scheduled. ECC HW generates decode IRQ each sector, so there will have more than one decode IRQ if read one page of large page NAND. Currently, ECC IRQ handle flow is that we will check whether it is decode IRQ at first by reading the register ECC_DECIRQ_STA. This is a read-clear type register. If this IRQ is decode IRQ, then the ECC IRQ signal will be cleared at the same time. Secondly, we will check whether all sectors are decoded by reading the register ECC_DECDONE. This is because the current IRQ may be not dealed in time, and the next sectors have been decoded before reading the register ECC_DECIRQ_STA. Then, the next sectors's decode IRQs will not be generated. Thirdly, if all sectors are decoded by comparing with ecc->sectors, then we will complete ecc->done, set ecc->sectors as 0, and disable ECC IRQ by programming the register ECC_IRQ_REG(op) as 0. Otherwise, wait for the next ECC IRQ. But, there is a timing issue between step one and two. When we read the reigster ECC_DECIRQ_STA, all sectors are decoded except the last sector, and the ECC IRQ signal is cleared. But the last sector is decoded before reading ECC_DECDONE, so the ECC IRQ signal is enabled again by ECC HW, and it means we will receive one extra ECC IRQ later. In step three, we will find that all sectors were decoded, then disable ECC IRQ and return. When deal with the extra ECC IRQ, the ECC IRQ status cannot be cleared anymore. That is because the register ECC_DECIRQ_STA can only be cleared when the register ECC_IRQ_REG(op) is enabled. But actually we have disabled ECC IRQ in the previous ECC IRQ handle. So, there will keep receiving ECC decode IRQ. Now, we read the register ECC_DECIRQ_STA once again before completing the ecc done event. This ensures that there will be no extra ECC decode IRQ. Also, remove writel(0, ecc->regs + ECC_IRQ_REG(op)) from irq handler, because ECC IRQ is disabled in mtk_ecc_disable(). And clear ECC_DECIRQ_STA in mtk_ecc_disable() in case there is a timeout to wait decode IRQ. Fixes: 1d6b1e46 ("mtd: mediatek: driver for MTK Smart Device") Cc: <stable@vger.kernel.org> Signed-off-by: NXiaolei Li <xiaolei.li@mediatek.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Xiaolei Li 提交于
There will get mtk ecc handler during mtk nand probe now. If mtk ecc module is not initialized, then mtk nand probe will return -EPROBE_DEFER, and retry later. Change the compile sequence of mtk_nand.o and mtk_ecc.o, initialize mtk ecc module before mtk nand module. This makes mtk nand module initialized as soon as possible. Signed-off-by: NXiaolei Li <xiaolei.li@mediatek.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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- 27 10月, 2017 1 次提交
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由 Roger Quadros 提交于
Since v4.12, NAND subpage writes were causing a NULL pointer dereference on OMAP platforms (omap2-nand) using OMAP_ECC_BCH4_CODE_HW, OMAP_ECC_BCH8_CODE_HW and OMAP_ECC_BCH16_CODE_HW. This is because for those ECC modes, omap_calculate_ecc_bch() generates ECC bytes for the entire (multi-sector) page and this can overflow the ECC buffer provided by nand_write_subpage_hwecc() as it expects ecc.calculate() to return ECC bytes for just one sector. However, the root cause of the problem is present since v3.9 but was not seen then as NAND buffers were being allocated as one big chunk prior to commit 3deb9979 ("mtd: nand: allocate aligned buffers if NAND_OWN_BUFFERS is unset"). Fix the issue by providing a OMAP optimized write_subpage() implementation. Fixes: 62116e51 ("mtd: nand: omap2: Support for hardware BCH error correction.") Cc: <stable@vger.kernel.org> Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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- 16 10月, 2017 2 次提交
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由 Sascha Hauer 提交于
When a struct device * is around use dev_dbg instead of pr_debug to give the messages more context. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Sascha Hauer 提交于
Having bad ECC is a normal case for NAND, do not spam log with the message. Users like UBI will print a message anyway which is more useful since it contains the PEB number that has bad ECC. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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- 14 10月, 2017 4 次提交
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由 Ladislav Michl 提交于
commit 67ce04bf ("mtd: nand: add OMAP2/OMAP3 NAND driver") assigned pointer to omap_nand_info to the platform drvdata in probe function just to be reasigned later to the pointer to mtd_info, which is what remove function expects it to be. Remove useless assignment. Signed-off-by: NLadislav Michl <ladis@linux-mips.org> Acked-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Ladislav Michl 提交于
As driver is now configured using DT, omap_nand_platform_data structure is no longer needed. Signed-off-by: NLadislav Michl <ladis@linux-mips.org> Acked-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Boris Brezillon 提交于
commit 6e532afa ("mtd: nand: atmel: Add PM ops") was defining PM ops but nothing was using/referencing those PM ops. Fixes: 6e532afa ("mtd: nand: atmel: Add PM ops") Cc: <stable@vger.kernel.org> Cc: Romain Izard <romain.izard.pro@gmail.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Acked-by: NWenyou Yang <wenyou.yang@microchip.com> Tested-by: NRomain Izard <romain.izard.pro@gmail.com>
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由 Boris Brezillon 提交于
Commit 6e532afa ("mtd: nand: atmel: Add PM ops") started to use the nand_reset() function which was not yet exported by the NAND framework (because it was only used internally before that). Export this symbol to avoid build errors when the driver is enabled as a module. Fixes: 6e532afa ("mtd: nand: atmel: Add PM ops") Cc: <stable@vger.kernel.org> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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- 07 10月, 2017 8 次提交
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由 Miquel Raynal 提交于
Marvell recent SoCs like A7k/A8k do not boot with NAND flash controller activated by default. Enabling the controller is a matter of writing in a system controller register that may also be used for other NAND related choices. This change is needed to stay bootloader independent. Signed-off-by: NMiquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Geert Uytterhoeven 提交于
Use the of_device_get_match_data() helper instead of open coding. While at it, make config const so the cast can be dropped. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Masahiro Yamada 提交于
The WE_2_RE register specifies the number of clock cycles inserted between the rising edge of #WE and the falling edge of #RE. The current setup_data_interface implementation takes care of tWHR, but tCCS is missing. Wait for max(tCSS, tWHR) to meet the spec. With setup_data_interface() properly programmed, the Denali NAND controller can observe the timing, so NAND_WAIT_TCCS flag is unneeded. Clarify this in the comment block. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Gregory CLEMENT 提交于
More and more SoCs use the pxa3xx_nand driver for their controller but the list of them was not updated. This patch add the last SoCs using the driver. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Romain Izard 提交于
During backup mode, the contents of all registers will be cleared as the SoC will be completely powered down. For a product that boots on NAND Flash memory, the bootloader will obviously use the related controller to read the Flash and correct any detected error in the memory, before handling back control to the kernel's resuming entry point. But it does not clean the NAND controller registers after use and on its side the kernel driver expects the error locator to be powered down and in a clean state. Add a resume hook for the PMECC error locator, and reset its registers. Signed-off-by: NRomain Izard <romain.izard.pro@gmail.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Abhishek Sahu 提交于
1. Add the function for command descriptor preparation which will be used only by BAM DMA and it will form the DMA descriptors containing command elements 2. DMA_PREP_CMD flag should be used for forming command DMA descriptors Reviewed-by: NArchit Taneja <architt@codeaurora.org> Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Abhishek Sahu 提交于
All the QPIC register read/write through BAM DMA requires command descriptor which contains the array of command elements. Reviewed-by: NArchit Taneja <architt@codeaurora.org> Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Linus Walleij 提交于
There is exactly one board in the kernel that defines platform data for the GPIO NAND driver. Use the feature to provide a lookup table for the GPIOs in the board file so we can convert the driver as a whole to just use GPIO descriptors. After this we can cut the use of <linux/of_gpio.h> and use the GPIO descriptor management from <linux/gpio/consumer.h> alone to grab and use the GPIOs used in the driver. I also created a local struct device *dev in the probe() function because I was getting annoyed with all the &pdev->dev dereferencing. Cc: arm@kernel.org Cc: Mike Rapoport <rppt@linux.vnet.ibm.com> Cc: Frans Klaver <fransklaver@gmail.com> Cc: Gerhard Sittig <gsi@denx.de> Cc: Jamie Iles <jamie.iles@oracle.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Reviewed-by: NMarek Vasut <marek.vasut@gmail.com> Acked-by: NJamie Iles <jamie.iles@oracle.com> Acked-by: NOlof Johansson <olof@lixom.net> Acked-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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- 27 9月, 2017 1 次提交
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由 Richard Genoud 提交于
When calculating the size needed by struct atmel_pmecc_user *user, the dmu and delta buffer sizes were forgotten. This lead to a memory corruption (especially with a large ecc_strength). Link: http://lkml.kernel.org/r/1506503157.3016.5.camel@gmail.com Fixes: f88fc122 ("mtd: nand: Cleanup/rework the atmel_nand driver") Cc: stable@vger.kernel.org Reported-by: NRichard Genoud <richard.genoud@gmail.com> Pointed-at-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: NRichard Genoud <richard.genoud@gmail.com> Reviewed-by: NNicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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- 22 9月, 2017 2 次提交
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由 Masahiro Yamada 提交于
The previous commit added some hooks into struct denali_nand_info, so here is one more for clean-up. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Masahiro Yamada 提交于
The Denali NAND IP core decodes the lower 28 bits of the slave address to get the control information; bit[27:26]=mode, bit[25:24]=bank, etc. This means 256MB address range must be allocated for this IP. (Direct Addressing) For systems with address space limitation, the Denali IP provides an optional module that translates the addressing - address and data are latched by the registers in the translation module. (Indexed Addressing) The addressing mode can be selected when the delivered RTL is configured, and it can be read out from the FEATURES register. Most of SoC vendors would choose Indexed Addressing to save the address space, but Direct Addressing is possible as well, and it can be easily supported by adding ->host_{read,write} hooks. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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