1. 28 7月, 2014 26 次提交
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      KVM: PPC: Book3S: Add hack for split real mode · c01e3f66
      Alexander Graf 提交于
      Today we handle split real mode by mapping both instruction and data faults
      into a special virtual address space that only exists during the split mode
      phase.
      
      This is good enough to catch 32bit Linux guests that use split real mode for
      copy_from/to_user. In this case we're always prefixed with 0xc0000000 for our
      instruction pointer and can map the user space process freely below there.
      
      However, that approach fails when we're running KVM inside of KVM. Here the 1st
      level last_inst reader may well be in the same virtual page as a 2nd level
      interrupt handler.
      
      It also fails when running Mac OS X guests. Here we have a 4G/4G split, so a
      kernel copy_from/to_user implementation can easily overlap with user space
      addresses.
      
      The architecturally correct way to fix this would be to implement an instruction
      interpreter in KVM that kicks in whenever we go into split real mode. This
      interpreter however would not receive a great amount of testing and be a lot of
      bloat for a reasonably isolated corner case.
      
      So I went back to the drawing board and tried to come up with a way to make
      split real mode work with a single flat address space. And then I realized that
      we could get away with the same trick that makes it work for Linux:
      
      Whenever we see an instruction address during split real mode that may collide,
      we just move it higher up the virtual address space to a place that hopefully
      does not collide (keep your fingers crossed!).
      
      That approach does work surprisingly well. I am able to successfully run
      Mac OS X guests with KVM and QEMU (no split real mode hacks like MOL) when I
      apply a tiny timing probe hack to QEMU. I'd say this is a win over even more
      broken split real mode :).
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      c01e3f66
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      KVM: PPC: Book3S: Stop PTE lookup on write errors · 2e27ecc9
      Alexander Graf 提交于
      When a page lookup failed because we're not allowed to write to the page, we
      should not overwrite that value with another lookup on the second PTEG which
      will return "page not found". Instead, we should just tell the caller that we
      had a permission problem.
      
      This fixes Mac OS X guests looping endlessly in page lookup code for me.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      2e27ecc9
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      KVM: PPC: Deflect page write faults properly in kvmppc_st · 17824b5a
      Alexander Graf 提交于
      When we have a page that we're not allowed to write to, xlate() will already
      tell us -EPERM on lookup of that page. With the code as is we change it into
      a "page missing" error which a guest may get confused about. Instead, just
      tell the caller about the -EPERM directly.
      
      This fixes Mac OS X guests when run with DCBZ32 emulation.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      17824b5a
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      KVM: PPC: Book3S: Move vcore definition to end of kvm_arch struct · 1287cb3f
      Alexander Graf 提交于
      When building KVM with a lot of vcores (NR_CPUS is big), we can potentially
      get out of the ld immediate range for dereferences inside that struct.
      
      Move the array to the end of our kvm_arch struct. This fixes compilation
      issues with NR_CPUS=2048 for me.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      1287cb3f
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      KVM: PPC: e500: Emulate power management control SPR · debf27d6
      Mihai Caraman 提交于
      For FSL e6500 core the kernel uses power management SPR register (PWRMGTCR0)
      to enable idle power down for cores and devices by setting up the idle count
      period at boot time. With the host already controlling the power management
      configuration the guest could simply benefit from it, so emulate guest request
      as a general store.
      Signed-off-by: NMihai Caraman <mihai.caraman@freescale.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      debf27d6
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      KVM: PPC: Book3S HV: Enable for little endian hosts · 6947f948
      Alexander Graf 提交于
      Now that we've fixed all the issues that HV KVM code had on little endian
      hosts, we can enable it in the kernel configuration for users to play with.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      6947f948
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      KVM: PPC: Book3S HV: Fix ABIv2 on LE · 9bf163f8
      Alexander Graf 提交于
      For code that doesn't live in modules we can just branch to the real function
      names, giving us compatibility with ABIv1 and ABIv2.
      
      Do this for the compiled-in code of HV KVM.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      9bf163f8
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      KVM: PPC: Book3S HV: Access XICS in BE · 76d072fb
      Alexander Graf 提交于
      On the exit path from the guest we check what type of interrupt we received
      if we received one. This means we're doing hardware access to the XICS interrupt
      controller.
      
      However, when running on a little endian system, this access is byte reversed.
      
      So let's make sure to swizzle the bytes back again and virtually make XICS
      accesses big endian.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      76d072fb
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      KVM: PPC: Book3S HV: Access host lppaca and shadow slb in BE · 0865a583
      Alexander Graf 提交于
      Some data structures are always stored in big endian. Among those are the LPPACA
      fields as well as the shadow slb. These structures might be shared with a
      hypervisor.
      
      So whenever we access those fields, make sure we do so in big endian byte order.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      0865a583
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      KVM: PPC: Book3S HV: Access guest VPA in BE · 02407552
      Alexander Graf 提交于
      There are a few shared data structures between the host and the guest. Most
      of them get registered through the VPA interface.
      
      These data structures are defined to always be in big endian byte order, so
      let's make sure we always access them in big endian.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      02407552
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      KVM: PPC: Book3S HV: Make HTAB code LE host aware · 6f22bd32
      Alexander Graf 提交于
      When running on an LE host all data structures are kept in little endian
      byte order. However, the HTAB still needs to be maintained in big endian.
      
      So every time we access any HTAB we need to make sure we do so in the right
      byte order. Fix up all accesses to manually byte swap.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      6f22bd32
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      PPC: Add asm helpers for BE 32bit load/store · 8f6822c4
      Alexander Graf 提交于
      From assembly code we might not only have to explicitly BE access 64bit values,
      but sometimes also 32bit ones. Add helpers that allow for easy use of lwzx/stwx
      in their respective byte-reverse or native form.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      8f6822c4
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      KVM: PPC: e500: Fix default tlb for victim hint · d57cef91
      Mihai Caraman 提交于
      Tlb search operation used for victim hint relies on the default tlb set by the
      host. When hardware tablewalk support is enabled in the host, the default tlb is
      TLB1 which leads KVM to evict the bolted entry. Set and restore the default tlb
      when searching for victim hint.
      Signed-off-by: NMihai Caraman <mihai.caraman@freescale.com>
      Reviewed-by: NScott Wood <scottwood@freescale.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      d57cef91
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      KVM: PPC: Book3S HV: Add H_SET_MODE hcall handling · 9642382e
      Michael Neuling 提交于
      This adds support for the H_SET_MODE hcall.  This hcall is a
      multiplexer that has several functions, some of which are called
      rarely, and some which are potentially called very frequently.
      Here we add support for the functions that set the debug registers
      CIABR (Completed Instruction Address Breakpoint Register) and
      DAWR/DAWRX (Data Address Watchpoint Register and eXtension),
      since they could be updated by the guest as often as every context
      switch.
      
      This also adds a kvmppc_power8_compatible() function to test to see
      if a guest is compatible with POWER8 or not.  The CIABR and DAWR/X
      only exist on POWER8.
      Signed-off-by: NMichael Neuling <mikey@neuling.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      9642382e
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      KVM: PPC: Book3S: Allow only implemented hcalls to be enabled or disabled · ae2113a4
      Paul Mackerras 提交于
      This adds code to check that when the KVM_CAP_PPC_ENABLE_HCALL
      capability is used to enable or disable in-kernel handling of an
      hcall, that the hcall is actually implemented by the kernel.
      If not an EINVAL error is returned.
      
      This also checks the default-enabled list of hcalls and prints a
      warning if any hcall there is not actually implemented.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      ae2113a4
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      KVM: PPC: Book3S: Controls for in-kernel sPAPR hypercall handling · 699a0ea0
      Paul Mackerras 提交于
      This provides a way for userspace controls which sPAPR hcalls get
      handled in the kernel.  Each hcall can be individually enabled or
      disabled for in-kernel handling, except for H_RTAS.  The exception
      for H_RTAS is because userspace can already control whether
      individual RTAS functions are handled in-kernel or not via the
      KVM_PPC_RTAS_DEFINE_TOKEN ioctl, and because the numeric value for
      H_RTAS is out of the normal sequence of hcall numbers.
      
      Hcalls are enabled or disabled using the KVM_ENABLE_CAP ioctl for the
      KVM_CAP_PPC_ENABLE_HCALL capability on the file descriptor for the VM.
      The args field of the struct kvm_enable_cap specifies the hcall number
      in args[0] and the enable/disable flag in args[1]; 0 means disable
      in-kernel handling (so that the hcall will always cause an exit to
      userspace) and 1 means enable.  Enabling or disabling in-kernel
      handling of an hcall is effective across the whole VM.
      
      The ability for KVM_ENABLE_CAP to be used on a VM file descriptor
      on PowerPC is new, added by this commit.  The KVM_CAP_ENABLE_CAP_VM
      capability advertises that this ability exists.
      
      When a VM is created, an initial set of hcalls are enabled for
      in-kernel handling.  The set that is enabled is the set that have
      an in-kernel implementation at this point.  Any new hcall
      implementations from this point onwards should not be added to the
      default set without a good reason.
      
      No distinction is made between real-mode and virtual-mode hcall
      implementations; the one setting controls them both.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      699a0ea0
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      KVM: PPC: e500mc: Enhance tlb invalidation condition on vcpu schedule · 1f0eeb7e
      Mihai Caraman 提交于
      On vcpu schedule, the condition checked for tlb pollution is too loose.
      The tlb entries of a vcpu become polluted (vs stale) only when a different
      vcpu within the same logical partition runs in-between. Optimize the tlb
      invalidation condition keeping last_vcpu per logical partition id.
      
      With the new invalidation condition, a guest shows 4% performance improvement
      on P5020DS while running a memory stress application with the cpu oversubscribed,
      the other guest running a cpu intensive workload.
      
      Guest - old invalidation condition
        real 3.89
        user 3.87
        sys 0.01
      
      Guest - enhanced invalidation condition
        real 3.75
        user 3.73
        sys 0.01
      
      Host
        real 3.70
        user 1.85
        sys 0.00
      
      The memory stress application accesses 4KB pages backed by 75% of available
      TLB0 entries:
      
      char foo[ENTRIES][4096] __attribute__ ((aligned (4096)));
      
      int main()
      {
      	char bar;
      	int i, j;
      
      	for (i = 0; i < ITERATIONS; i++)
              	for (j = 0; j < ENTRIES; j++)
                  		bar = foo[j][0];
      
      	return 0;
      }
      Signed-off-by: NMihai Caraman <mihai.caraman@freescale.com>
      Reviewed-by: NScott Wood <scottwood@freescale.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      1f0eeb7e
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      KVM: PPC: Book3S PR: Fix sparse endian checks · f396df35
      Alexander Graf 提交于
      While sending sparse with endian checks over the code base, it triggered at
      some places that were missing casts or had wrong types. Fix them up.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      f396df35
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      KVM: PPC: Book3S PR: Fix ABIv2 on LE · da166fac
      Alexander Graf 提交于
      We switched to ABIv2 on Little Endian systems now which gets rid of the
      dotted function names. Branch to the actual functions when we see such
      a system.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      da166fac
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      KVM: PPC: Assembly functions exported to modules need _GLOBAL_TOC() · ad7d4584
      Anton Blanchard 提交于
      Both kvmppc_hv_entry_trampoline and kvmppc_entry_trampoline are
      assembly functions that are exported to modules and also require
      a valid r2.
      
      As such we need to use _GLOBAL_TOC so we provide a global entry
      point that establishes the TOC (r2).
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      ad7d4584
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      KVM: PPC: Book3S HV: Fix ABIv2 indirect branch issue · 05a308c7
      Anton Blanchard 提交于
      To establish addressability quickly, ABIv2 requires the target
      address of the function being called to be in r12.
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      05a308c7
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      KVM: PPC: Book3S PR: Handle hyp doorbell exits · 568fccc4
      Alexander Graf 提交于
      If we're running PR KVM in HV mode, we may get hypervisor doorbell interrupts.
      Handle those the same way we treat normal doorbells.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      568fccc4
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      KVM: PPC: Book3s HV: Fix tlbie compile error · f6bf3a66
      Alexander Graf 提交于
      Some compilers complain about uninitialized variables in the compute_tlbie_rb
      function. When you follow the code path you'll realize that we'll never get
      to that point, but the compiler isn't all that smart.
      
      So just default to 4k page sizes for everything, making the compiler happy
      and the code slightly easier to read.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Acked-by: NPaul Mackerras <paulus@samba.org>
      f6bf3a66
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      KVM: PPC: Book3s PR: Disable AIL mode with OPAL · fb4188ba
      Alexander Graf 提交于
      When we're using PR KVM we must not allow the CPU to take interrupts
      in virtual mode, as the SLB does not contain host kernel mappings
      when running inside the guest context.
      
      To make sure we get good performance for non-KVM tasks but still
      properly functioning PR KVM, let's just disable AIL whenever a vcpu
      is scheduled in.
      
      This is fundamentally different from how we deal with AIL on pSeries
      type machines where we disable AIL for the whole machine as soon as
      a single KVM VM is up.
      
      The reason for that is easy - on pSeries we do not have control over
      per-cpu configuration of AIL. We also don't want to mess with CPU hotplug
      races and AIL configuration, so setting it per CPU is easier and more
      flexible.
      
      This patch fixes running PR KVM on POWER8 bare metal for me.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Acked-by: NPaul Mackerras <paulus@samba.org>
      fb4188ba
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      KVM: PPC: BOOK3S: PR: Emulate instruction counter · 06da28e7
      Aneesh Kumar K.V 提交于
      Writing to IC is not allowed in the privileged mode.
      Signed-off-by: NAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      06da28e7
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      KVM: PPC: BOOK3S: PR: Emulate virtual timebase register · 8f42ab27
      Aneesh Kumar K.V 提交于
      virtual time base register is a per VM, per cpu register that needs
      to be saved and restored on vm exit and entry. Writing to VTB is not
      allowed in the privileged mode.
      Signed-off-by: NAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
      [agraf: fix compile error]
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      8f42ab27
  2. 06 7月, 2014 1 次提交
  3. 30 6月, 2014 11 次提交
  4. 26 6月, 2014 1 次提交
  5. 19 6月, 2014 1 次提交