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  1. 09 7月, 2007 4 次提交
  3. 26 4月, 2007 2 次提交
  5. 04 4月, 2007 1 次提交
    • B
      b44: fix IFF_ALLMULTI handling of CAM slots · cda22aa9
      由 Bill Helfinstine 提交于 
      If you set the IFF_ALLMULTI flag on a b44 device, or if you join more than
B44_MCAST_TABLE_SIZE multicast groups, the device will stop receiving unicast
messages.  This is because the __b44_set_mac_addr call sets the zeroth CAM
entry to the MAC address of the device, and then the loop at line 1722
proceeds to overwrite it unless the value of i is set by the __b44_load_mcast
call.  However, when IFF_ALLMULTI is set, that call is bypassed, leaving i set
to zero.

Fixed by starting the loop at 1 to make it skip the CAM entry for the MAC
address.
Signed-off-by: NBill Helfinstine <bhelf@flitterfly.whirpon.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      cda22aa9
  7. 18 2月, 2007 2 次提交
    • G
      B44: increase wait loop · 40ee8c76
      由 Gary Zambrano 提交于 
      The b44 Enet control disable bit may take longer to clear on some
systems, so the loop count is increased with this patch. Functionality
is not compromised, but a debug message can be seen when the bit is not
cleared within the count value.
Thanks to Vasileios Lourdas who reported the problem.

Signed-off by: Gary Zambrano <zambrano@broadcom.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      40ee8c76
    • G
      b44: replace define · 97db9ee7
      由 Gary Zambrano 提交于 
      Replaced B44_DMA_MASK with DMA_30BIT_MASK.

Signed-off by: Gary Zambrano <zambrano@broadcom.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      97db9ee7
  9. 07 2月, 2007 1 次提交
  11. 31 1月, 2007 1 次提交
  13. 30 1月, 2007 3 次提交
  15. 27 12月, 2006 1 次提交
  17. 07 11月, 2006 1 次提交
  19. 11 10月, 2006 1 次提交
    • M
      [PATCH] b44: fix eeprom endianess issue · 6f627683
      由 Michael Buesch 提交于 
      This fixes eeprom read on big-endian architectures.

readw returns the data in CPU order.  With cpu_to_le16 we convert it to little
endian, because "ptr" is a pointer to a _byte_ arrray.  See the cast above.  A
byte array is little endian.

The bug is:

Reading u16 values with readw, casting them into an u8 array and accessing
this u8 array as an u8 (byte) array.  The correct fix is to swap the
CPU-ordering value returned by readw into little endian, as the u8 array is
little endian.

This compiles to nothing on little endian hardware (so it does not change b44
code on LE hardware), but _fixes_ code on BE hardware.
Signed-off-by: NMichael Buesch <mb@bu3sch.de>
Cc: Jeff Garzik <jeff@garzik.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      6f627683
  21. 05 10月, 2006 2 次提交
    • D
      IRQ: Maintain regs pointer globally rather than passing to IRQ handlers · 7d12e780
      由 David Howells 提交于 
      Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.

The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around.  On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).

Where appropriate, an arch may override the generic storage facility and do
something different with the variable.  On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.

Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions.  Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller.  A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.

I've build this code with allyesconfig for x86_64 and i386.  I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.

This will affect all archs.  Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:

	struct pt_regs *old_regs = set_irq_regs(regs);

And put the old one back at the end:

	set_irq_regs(old_regs);

Don't pass regs through to generic_handle_irq() or __do_IRQ().

In timer_interrupt(), this sort of change will be necessary:

	-	update_process_times(user_mode(regs));
	-	profile_tick(CPU_PROFILING, regs);
	+	update_process_times(user_mode(get_irq_regs()));
	+	profile_tick(CPU_PROFILING);

I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().

Some notes on the interrupt handling in the drivers:

 (*) input_dev() is now gone entirely.  The regs pointer is no longer stored in
     the input_dev struct.

 (*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking.  It does
     something different depending on whether it's been supplied with a regs
     pointer or not.

 (*) Various IRQ handler function pointers have been moved to type
     irq_handler_t.
Signed-Off-By: NDavid Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
      7d12e780
    • J
      [netdrvr] b44: handle excessive multicast groups · 2f614fe0
      由 Jeff Garzik 提交于 
      If there are more than B44_MCAST_TABLE_SIZE groups in the dev->mc_list,
it will only listen to the first B44_MCAST_TABLE_SIZE that it sees.

This change makes the driver go into RXCONFIG_ALLMULTI mode if there
are more than B44_MCAST_TABLE_SIZE groups being subscribed to, similar
to other network drivers.

Noticed by Bill Helfinstine <bhelf@flitterfly.whirpon.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      2f614fe0
  23. 14 9月, 2006 1 次提交
  25. 20 8月, 2006 1 次提交
  27. 06 7月, 2006 2 次提交
  29. 03 7月, 2006 1 次提交
  31. 23 6月, 2006 5 次提交
  33. 16 5月, 2006 2 次提交
  35. 13 4月, 2006 3 次提交
  37. 02 4月, 2006 1 次提交
  39. 30 3月, 2006 2 次提交
  41. 27 1月, 2006 1 次提交
  43. 18 1月, 2006 1 次提交
  45. 01 12月, 2005 1 次提交