- 30 11月, 2012 1 次提交
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由 Xi Wang 提交于
The macro bit(n) is defined as ((u32)1 << n), and thus it doesn't work with n >= 32, such as in mvs_94xx_assign_reg_set(): if (i >= 32) { mvi->sata_reg_set |= bit(i); ... } The shift ((u32)1 << n) with n >= 32 also leads to undefined behavior. The result varies depending on the architecture. This patch changes bit(n) to do a 64-bit shift. It also simplifies mv_ffc64() using __ffs64(), since invoking ffz() with ~0 is undefined. Signed-off-by: NXi Wang <xi.wang@gmail.com> Acked-by: NXiangliang Yu <yuxiangl@marvell.com> Cc: stable@vger.kernel.org Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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- 26 7月, 2011 5 次提交
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由 Xiangliang Yu 提交于
Remove obsolete comments and add new comments Signed-off-by: NXiangliang Yu <yuxiangl@marvell.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Xiangliang Yu 提交于
Change code to match HBA datasheet. Change code to make it readable. Add support big endian for mvs_prd_imt. Add cpu_to_le32 and cpu_to_le64 to use on addr. Add scan_finished for structure mvs_prv_info. Signed-off-by: NXiangliang Yu <yuxiangl@marvell.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Xiangliang Yu 提交于
Add new macros: MVS_SOFT_RESET, MVS_HARD_RESET, MVS_PHY_TUNE, MVS_COMMAND_ACTIVE, EXP_BRCT_CHG, MVS_MAX_SG Add new member sg_width in struct mvs_chip_info Use macros rather than magic number Add new functions: mvs_fill_ssp_resp_iu, mvs_set_sense, mvs_94xx_clear_srs_irq, mvs_94xx_phy_set_link_rate Signed-off-by: NXiangliang Yu <yuxiangl@marvell.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Xiangliang Yu 提交于
Remove unused macros: VSR_PHY_VS0, VSR_PHY_VS1, MVS_SLOTS, MVS_CAN_QUEUE, MVS_MSI, SG_MX, _MV_DUMP, MV_DISABLE_NCQ Remove unused variables for mvs_info: irq, exp_req, cmd_size Remove unused functions: mvs_get_sas_addr, mvs_hexdump, mvs_hba_sb_dump, mvs_hab_memory_dump, mvs_hba_cq_dump Signed-off-by: NXiangliang Yu <yuxiangl@marvell.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Xiangliang Yu 提交于
Add 94xx phy tuning to aid manufacturing. Add support for 94xx multiple revisions: A0, B0, C0, C1, C2. Signed-off-by: NXiangliang Yu <yuxiangl@marvell.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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- 02 5月, 2011 1 次提交
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由 Xiangliang Yu 提交于
1. Add support for Task collector mode. 2. Fixed relative collector mode bug: - I/O failed when disks is on two ports - system hang when hotplug disk - system hang when unplug disk during run IO 3. Unlock ap->lock within .lldd_execute_task for direct mode to improve performance Signed-off-by: NXiangliang Yu <yuxiangl@marvell.com> Signed-off-by: NJames Bottomley <James.Bottomley@suse.de>
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- 21 5月, 2009 1 次提交
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由 Andy Yan 提交于
This version contains following main changes - Switch to new layout to support more types of ASIC. - SSP TMF supported and related Error Handing enhanced. - Support flash feature with delay 2*HZ when PHY changed. - Support Marvell 94xx series ASIC for 6G SAS/SATA, which has 2 88SE64xx chips but any different register description. - Support SPI flash for HBA-related configuration info. - Other patch enhanced from kernel side such as increasing PHY type [jejb: fold back in DMA_BIT_MASK changes] Signed-off-by: NYing Chu <jasonchu@marvell.com> Signed-off-by: NAndy Yan <ayan@marvell.com> Signed-off-by: NKe Wei <kewei@marvell.com> Signed-off-by: NJeff Garzik <jgarzik@redhat.com> Signed-off-by: NJames Bottomley <James.Bottomley@HansenPartnership.com>
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