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  1. 24 4月, 2015 1 次提交
  3. 23 4月, 2015 1 次提交
    • C
      spi: fsl-spi: use devm_ioremap_resource() to map parameter ram on CPM1 · 575bec53
      由 Christophe Leroy 提交于 
      On CPM2, the SPI parameter RAM is dynamically allocated in the
dualport RAM whereas in CPM1, it is statically allocated to a default
address with capability to relocate it somewhere else via the use of
CPM micropatch. The address of the parameter RAM is given by the boot
loader and expected to be mapped via devm_ioremap_resource()

In the current implementation, in function fsl_spi_cpm_get_pram()
there is a confusion between the SPI_BASE register and the base of the
SPI parameter RAM. Fortunatly, it is working properly with MPC866 and
MPC885 because they do set SPI_BASE, but on MPC860 and other old
MPC8xx that doesn't set SPI_BASE, pram_ofs is not properly set.
Also, the parameter RAM is not properly mapped with
devm_ioremap_resource() as it should but still gets accessible by
chance through the full RAM which is mapped from somewhere else.

This patch applies to the SPI driver the same principle as for the
CPM UART: when the CPM is of type CPM1, we simply do an
devm_ioremap_resource() of the area provided via the device tree.
Signed-off-by: NChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: NMark Brown <broonie@kernel.org>
      575bec53
  5. 18 4月, 2015 1 次提交
  7. 17 4月, 2015 2 次提交
    • R
      spi: check tx_buf and rx_buf in spi_unmap_msg · f8bb820d
      由 Robin Gong 提交于 
      Some spi device drivers use the same tx_buf and rx_buf repeatly for better
performance such as driver/input/touchsreen/ads7846.c, but spi core grab tx_buf
/rx_buf of transfer and set them as dummy_tx/dummy_rx once they are NULL. Thus,
in the second time the tx_buf/rx_buf will be replaced by dummy_tx/dummy_rx and
the data which produced by the last tx or rx may be wrongly sent to the device
or handled by the upper level protocol. This patch just keep the orignal value
of tx_buf/rx_buf if they are NULL after this transfer processed.
Signed-off-by: NRobin Gong <b38343@freescale.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
      f8bb820d
    • M
      spi: bcm2835: change timeout of polling driver to 1s · 145367ba
      由 Martin Sperl 提交于 
      The way that the timeout code is written in the polling function
the timeout does also trigger when interrupted or rescheduled while
in the polling loop.

This patch changes the timeout from effectively 20ms (=2 jiffies) to
1 second and removes the time that the transfer really takes out of
the computation, as - per design - this is <30us and the jiffie resolution
is 10ms so that does not make any difference what so ever.
Signed-off-by: NMartin Sperl <kernel@martin.sperl.org>
Signed-off-by: NMark Brown <broonie@kernel.org>
      145367ba
  9. 15 4月, 2015 1 次提交
    • G
      spi: bcm2835: Add GPIOLIB dependency · 8844d0f1
      由 Guenter Roeck 提交于 
      Fix:

drivers/spi/spi-bcm2835.c: In function 'chip_match_name':
drivers/spi/spi-bcm2835.c:356:21: error:
			dereferencing pointer to incomplete type
drivers/spi/spi-bcm2835.c: In function 'bcm2835_spi_setup':
drivers/spi/spi-bcm2835.c:382:2: error:
	`		implicit declaration of function 'gpiochip_find'
drivers/spi/spi-bcm2835.c:387:21: error:
			dereferencing pointer to incomplete type

by adding the now mandatory GPIOLIB dependency.

Fixes: a30a555d ("spi: bcm2835: transform native-cs to gpio-cs
	on first spi_setup")
Cc: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NMark Brown <broonie@kernel.org>
      8844d0f1
  11. 11 4月, 2015 2 次提交
    • M
      spi: bcm2835: enabling polling mode for transfers shorter than 30us · 704f32d4
      由 Martin Sperl 提交于 
      In cases of short transfer times the CPU is spending lots of time
in the interrupt handler and scheduler to reschedule the worker thread.

Measurements show that we have times where it takes 29.32us to between
the last clock change and the time that the worker-thread is running again
returning from wait_for_completion_timeout().

During this time the interrupt-handler is running calling complete()
and then also the scheduler is rescheduling the worker thread.

This time can vary depending on how much of the code is still in
CPU-caches, when there is a burst of spi transfers the subsequent delays
are in the order of 25us, so the value of 30us seems reasonable.

With polling the whole transfer of 4 bytes at 10MHz finishes after 6.16us
(CS down to up) with the real transfer (clock running) taking 3.56us.
So the efficiency has much improved and is also freeing CPU cycles,
reducing interrupts and context switches.

Because of the above 30us seems to be a reasonable limit for polling.
Signed-off-by: NMartin Sperl <kernel@martin.sperl.org>
Signed-off-by: NMark Brown <broonie@kernel.org>
      704f32d4
    • M
      spi: bcm2835: transform native-cs to gpio-cs on first spi_setup · a30a555d
      由 Martin Sperl 提交于 
      Transforms the bcm-2835 native SPI-chip select to their gpio-cs equivalent.

This allows for some support of some optimizations that are not
possible due to HW-gliches on the CS line - especially filling
the FIFO before enabling SPI interrupts (by writing to CS register)
while the transfer is already in progress (See commit: e3a2be30)

This patch also works arround some issues in bcm2835-pinctrl which does not
set the value when setting the GPIO as output - it just sets up output and
(typically) leaves the GPIO as low.  When a fix for this is merged then this
gpio_set_value can get removed from bcm2835_spi_setup.
Signed-off-by: NMartin Sperl <kernel@martin.sperl.org>
Signed-off-by: NMark Brown <broonie@kernel.org>
      a30a555d
  13. 09 4月, 2015 3 次提交
  15. 08 4月, 2015 2 次提交
  17. 07 4月, 2015 5 次提交
  19. 02 4月, 2015 2 次提交
    • L
      spi: imx: read back the RX/TX watermark levels earlier · f511ab09
      由 Lucas Stach 提交于 
      They are used to decide if the controller can do DMA on a buffer
of a specific length and thus are needed before any transfer is attempted.

This fixes a memory leak where the SPI core uses the drivers can_dma()
callback to determine if a buffer needs to be mapped. As the watermark
levels aren't correct at that point the driver falsely claims to be able to
DMA the buffer when it fact it isn't.
After the transfer has been done the core uses the same callback to
determine if it needs to unmap the buffers. As the driver now correctly
claims to not being able to DMA the buffer the core doesn't attempt to
unmap the buffer which leaves the SGT leaking.

Fixes: f62caccd (spi: spi-imx: add DMA support)
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NMark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
      f511ab09
    • C
      spi: spi-bfin5xx: Initialize cr_width in bfin_spi_pump_transfers() · 057f6061
      由 Chen Gang 提交于 
      cr_width may be not initialized before using by cr, the related warning
(with defconfig under blackfin by gcc5):

    CC      drivers/spi/spi-bfin5xx.o
  drivers/spi/spi-bfin5xx.c: In function 'bfin_spi_pump_transfers':
  drivers/spi/spi-bfin5xx.c:655:5: warning: 'cr_width' may be used uninitialized in this function [-Wmaybe-uninitialized]
    cr |= cr_width;
       ^
Signed-off-by: NChen Gang <gang.chen.5i5j@gmail.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
      057f6061
  21. 01 4月, 2015 1 次提交
  23. 31 3月, 2015 2 次提交
  25. 30 3月, 2015 3 次提交
  27. 28 3月, 2015 1 次提交
    • M
      spi: spidev: Warn loudly if instantiated from DT as "spidev" · 956b200a
      由 Mark Brown 提交于 
      Since spidev is a detail of how Linux controls a device rather than a
description of the hardware in the system we should never have a node
described as "spidev" in DT, any SPI device could be a spidev so this
is just not a useful description.

In order to help prevent users from writing such device trees generate a
warning if spidev is instantiated as a DT node without an ID in the match
table.
Signed-off-by: NMark Brown <broonie@kernel.org>
      956b200a
  29. 27 3月, 2015 3 次提交
    • M
      spi: bcm2835: move to the transfer_one driver model · e34ff011
      由 Martin Sperl 提交于 
      This also allows for GPIO-CS to get used removing the limitation of
2/3 SPI devises on the SPI bus.

Fixes: spi-cs-high with native CS with multiple devices on the spi-bus
resetting the chip selects to "normal" polarity after a finished
transfer.

No other functionality/improvements added.

Tested with the following 4 devices on the spi-bus:
* mcp2515 with native CS
* mcp2515 with gpio CS
* fb_st7735r with native CS
    (plus spi-cs-high via transistor inverting polarity)
* enc28j60 with gpio-CS
Tested-by: NMartin Sperl <kernel@martin.sperl.org>
Signed-off-by: NMartin Sperl <kernel@martin.sperl.org>
Signed-off-by: NMark Brown <broonie@kernel.org>
      e34ff011
    • J
      spi/rockchip: Add device tree property to configure Rx Sample Delay · 76b17e6e
      由 Julius Werner 提交于 
      We have found that we can sometimes see read failures on boards with
high-capacitance SPI lines. It seems that the controller samples the Rx
data line too early, and its register interface has an "Rx Sample Delay"
setting to fine-tune against this issue.

This patch adds a new optional device tree entry that can configure this
delay in terms of nanoseconds. The kernel will calculate the
best-fitting amount of parent clock ticks to program the controller with
based on that.
Signed-off-by: NJulius Werner <jwerner@chromium.org>
Signed-off-by: NMark Brown <broonie@kernel.org>
      76b17e6e
    • J
      spi/rockchip: Round up clock rate divisor to err on the safe side · 754ec43c
      由 Julius Werner 提交于 
      The Rockchip SPI driver currently calculates its clock rate divisor by
integer dividing the parent rate by the target rate, and then rounding
the result up to the next even number (since the divisor must be
even).

Clock rate divisors should always be rounded up, so that the resulting
frequency is lower or equal to the target. This is correctly done in the
second step here but not in the first, so we still have a risk of
exceeding the desired target frequency (e.g. setting spi-max-frequency
to 40000000 with a parent clock of 99000000 could lead to a divisor of
99000000 / 40000000 == 2 (which is even) that then results in an
effective frequency of 99000000 / 2 == 49500000 (potentially exceeding
the flash chip's specifications).

This patch changes the division to round up to fix this problem.
Signed-off-by: NJulius Werner <jwerner@chromium.org>
Signed-off-by: NMark Brown <broonie@kernel.org>
      754ec43c
  31. 26 3月, 2015 2 次提交
  33. 25 3月, 2015 2 次提交
  35. 24 3月, 2015 6 次提交