- 25 11月, 2020 3 次提交
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由 Likun Gao 提交于
Update golden setting for sienna_cichlid. Signed-off-by: NLikun Gao <Likun.Gao@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Gustavo A. R. Silva 提交于
In preparation to enable -Wimplicit-fallthrough for Clang, fix multiple warnings by explicitly adding multiple break statements instead of just letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115Signed-off-by: NGustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jinzhou Su 提交于
Using KIQ to map GFX queues instead of MMIO for gfx async ring, add missing doorbell range setting. v2: fix typo Signed-off-by: NJinzhou.Su <Jinzhou.Su@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 17 11月, 2020 1 次提交
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由 Likun Gao 提交于
Update golden setting for sienna_cichlid. Signed-off-by: NLikun Gao <Likun.Gao@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 13 11月, 2020 1 次提交
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由 Nirmoy Das 提交于
Compute queues are configurable with module param, num_kcq. amdgpu_gfx_is_high_priority_compute_queue was setting 1st 4 queues to high priority queue leaving a null drm scheduler in adev->gpu_sched[hw_ip]["normal_prio"].sched if num_kcq < 5. This patch tries to fix it by alternating compute queue priority between normal and high priority. Fixes: 33abcb1f (drm/amdgpu: set compute queue priority at mqd_init) Signed-off-by: NNirmoy Das <nirmoy.das@amd.com> Reviewed-by: NFelix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 11 11月, 2020 1 次提交
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由 Tao Zhou 提交于
Set LDS_CONFIG to 0x20 on dimgrey_cavefish to fix GPU hang. Signed-off-by: NTao Zhou <tao.zhou1@amd.com> Reviewed-by: NJiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 05 11月, 2020 3 次提交
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由 Marek Olšák 提交于
v2: squash in build fix Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NMarek Olšák <marek.olsak@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Tao Zhou 提交于
GFXOFF has been supported by PMFW, enable it directly in driver for dimgrey_cavefish. Signed-off-by: NTao Zhou <tao.zhou1@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jinzhou.Su 提交于
1. Add FGCG for gfx10 2. Get FGCG status for pm info debugfs Signed-off-by: NJinzhou.Su <Jinzhou.Su@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 04 11月, 2020 1 次提交
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由 Likun Gao 提交于
Update golden setting for sienna_cichlid. Signed-off-by: NLikun Gao <Likun.Gao@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 03 11月, 2020 2 次提交
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由 Deepak R Varma 提交于
General code indentation and alignment changes such as replace spaces by tabs or align function arguments as per the coding style guidelines. Issue reported by checkpatch script. Signed-off-by: NDeepak R Varma <mh12gx2825@gmail.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Likun Gao 提交于
Update golden setting for sienna_cichlid. Signed-off-by: NLikun Gao <Likun.Gao@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 30 10月, 2020 2 次提交
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由 Chengming Gui 提交于
Use ">= CHIP_SIENNA_CICHLID" to replace per asic check Signed-off-by: NChengming Gui <Jack.Gui@amd.com> Reviewed-by: NHawking.Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jinzhou.Su 提交于
Add RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK Signed-off-by: NJinzhou.Su <Jinzhou.Su@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 24 10月, 2020 1 次提交
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由 Likun Gao 提交于
Skip disabled sa to correct the cu_info and active_rbs for sienna cichlid. Signed-off-by: NLikun Gao <Likun.Gao@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 22 10月, 2020 4 次提交
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由 Likun Gao 提交于
Skip disabled sa to correct the cu_info and active_rbs for sienna cichlid. Signed-off-by: NLikun Gao <Likun.Gao@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 5.9.x
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由 Likun Gao 提交于
Update golden setting for sienna_cichlid. Signed-off-by: NLikun Gao <Likun.Gao@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 5.9.x
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由 Likun Gao 提交于
Support to load RLC iram and dram ucode when RLC firmware struct use v2.2 Signed-off-by: NLikun Gao <Likun.Gao@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Likun Gao 提交于
Add function for sienna_cichlid to force PBB workload mode to zero by checking whether there have SE been harvested. Signed-off-by: NLikun Gao <Likun.Gao@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 5.9.x
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- 17 10月, 2020 2 次提交
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由 Alex Deucher 提交于
Add a helper so we can set per asic default values. Also, the module parameter is currently clamped to 8, but clamp it per asic just in case some asics have different limits in the future. Enable the option on gfx6,7 as well for consistency. Acked-by: NNirmoy Das <nirmoy.das@amd.com> Reviewed-by: NFelix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Likun Gao 提交于
Update golden setting for sienna_cichlid. Signed-off-by: NLikun Gao <Likun.Gao@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 16 10月, 2020 5 次提交
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由 Likun Gao 提交于
Support to load RLC iram and dram ucode when RLC firmware struct use v2.2 Signed-off-by: NLikun Gao <Likun.Gao@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Likun Gao 提交于
Add function for sienna_cichlid to force PBB workload mode to zero by checking whether there have SE been harvested. Signed-off-by: NLikun Gao <Likun.Gao@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jiansong Chen 提交于
This reverts commit 39ad0824. TDR issue has been resovled by pmfw update. Signed-off-by: NJiansong Chen <Jiansong.Chen@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
Enable Navi1X MGCG perfmon setting. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Huang Rui 提交于
This patch fixes the gfx hang while use firmware direct loading mode. Signed-off-by: NHuang Rui <ray.huang@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 15 10月, 2020 1 次提交
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由 Huang Rui 提交于
The driver needn't load smu binary on APU platforms. Signed-off-by: NHuang Rui <ray.huang@amd.com> Reviewed-by: NKevin Wang <kevin1.wang@amd.com> Reviewed-by: NMadhav Chauhan <madhav.chauhan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 13 10月, 2020 7 次提交
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由 Tao Zhou 提交于
Add gc golden setting for dimgrey_cavefish. Signed-off-by: NTao Zhou <tao.zhou1@amd.com> Tested-by: NChengming Gui <Jack.Gui@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Tao Zhou 提交于
Same as sienna_cichlid, dimgrey_cavefish supports WAIT_REG_MEM packet. Signed-off-by: NTao Zhou <tao.zhou1@amd.com> Reviewed-by: NJiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Tao Zhou 提交于
pa_sc_tile_steering_override is only programmable for gfx10.0/10.1/10.2, the same as sienna_cichlid. Signed-off-by: NTao Zhou <tao.zhou1@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Tao Zhou 提交于
The gfx version of dimgrey_cavefish is 10.3, identical to sienna_cichlid, follow the way of sienna_cichlid. Signed-off-by: NTao Zhou <tao.zhou1@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: NJiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Tao Zhou 提交于
Enable gfx block for dimgrey_cavefish, same as navy_flounder. Signed-off-by: NTao Zhou <tao.zhou1@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: NJiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Tao Zhou 提交于
Set gfx clock gating for dimgrey_cavefish. Signed-off-by: NTao Zhou <tao.zhou1@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: NJiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Tao Zhou 提交于
Add support for dimgrey_cavefish cp/rlc firmware. Signed-off-by: NTao Zhou <tao.zhou1@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: NJiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 10 10月, 2020 1 次提交
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由 Changfeng 提交于
It needs to use adev->pg_flags other than adev->cg_glags in gfx_v10_cntl_power_gating Signed-off-by: NChangfeng <Changfeng.Zhu@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 06 10月, 2020 5 次提交
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由 Huang Rui 提交于
This patch adds power gating handler for gfx10. v2: simplify function Signed-off-by: NHuang Rui <ray.huang@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Huang Rui 提交于
GFXOFF will be enabled once it's verified on real asic. v2: move check into gfx10 module. Signed-off-by: NHuang Rui <ray.huang@amd.com> Reviewed-by: NAaron Liu <aaron.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Huang Rui 提交于
This patch is to add gfx golden settings for vangogh post si. v2: squash in updates v3: fix SPI register offset Signed-off-by: NHuang Rui <ray.huang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Huang Rui 提交于
Add van gogh checks to gfx10 code. v2: squash in fixes v3: fix mode Signed-off-by: NHuang Rui <ray.huang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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