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  1. 18 10月, 2021 2 次提交
  3. 01 9月, 2021 2 次提交
  5. 18 6月, 2021 5 次提交
  7. 09 4月, 2021 5 次提交
  9. 28 1月, 2021 2 次提交
  11. 30 11月, 2020 5 次提交
  13. 22 9月, 2020 5 次提交
  15. 25 7月, 2020 3 次提交
  17. 19 5月, 2020 2 次提交
  19. 24 3月, 2020 2 次提交
  21. 05 9月, 2019 2 次提交
  23. 29 4月, 2019 1 次提交
    • T
      habanalabs: Use single pool for CPU accessible host memory · 03d5f641
      由 Tomer Tayar 提交于 
      The device's CPU accessible memory on host is managed in a dedicated
pool, except for 2 regions - Primary Queue (PQ) and Event Queue (EQ) -
which are allocated from generic DMA pools.
Due to address length limitations of the CPU, the addresses of all these
memory regions must have the same MSBs starting at bit 40.
This patch modifies the allocation of the PQ and EQ to be also from the
dedicated pool, to ensure compliance with the limitation.
Signed-off-by: NTomer Tayar <ttayar@habana.ai>
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
      03d5f641
  25. 04 3月, 2019 2 次提交
  27. 18 2月, 2019 2 次提交
    • O
      habanalabs: add event queue and interrupts · 1251f23a
      由 Oded Gabbay 提交于 
      This patch adds support for receiving events from Goya's control CPU and
for receiving MSI-X interrupts from Goya's DMA engines and CPU.

Goya's PCI controller supports up to 8 MSI-X interrupts, which only 6 of
them are currently used. The first 5 interrupts are dedicated for Goya's
DMA engine queues. The 6th interrupt is dedicated for Goya's control CPU.

The DMA queue will signal its MSI-X entry upon each completion of a command
buffer that was placed on its primary queue. The driver will then mark that
CB as completed and free the related resources. It will also update the
command submission object which that CB belongs to.

There is a dedicated event queue (EQ) between the driver and Goya's control
CPU. The EQ is located on the Host memory. The control CPU writes a new
entry to the EQ for various reasons, such as ECC error, MMU page fault, Hot
temperature. After writing the new entry to the EQ, the control CPU will
trigger its dedicated MSI-X entry to signal the driver that there is a new
entry in the EQ. The driver will then read the entry and act accordingly.
Reviewed-by: NMike Rapoport <rppt@linux.ibm.com>
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      1251f23a
    • O
      habanalabs: add h/w queues module · 9494a8dd
      由 Oded Gabbay 提交于 
      This patch adds the H/W queues module and the code to initialize Goya's
various compute and DMA engines and their queues.

Goya has 5 DMA channels, 8 TPC engines and a single MME engine. For each
channel/engine, there is a H/W queue logic which is used to pass commands
from the user to the H/W. That logic is called QMAN.

There are two types of QMANs: external and internal. The DMA QMANs are
considered external while the TPC and MME QMANs are considered internal.
For each external queue there is a completion queue, which is located on
the Host memory.

The differences between external and internal QMANs are:

1. The location of the queue's memory. External QMANs are located on the
   Host memory while internal QMANs are located on the on-chip memory.

2. The external QMAN write an entry to a completion queue and sends an
   MSI-X interrupt upon completion of a command buffer that was given to
   it. The internal QMAN doesn't do that.
Reviewed-by: NMike Rapoport <rppt@linux.ibm.com>
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      9494a8dd