1. 23 8月, 2013 20 次提交
    • P
      drm/i915: fix SDEIMR assertion when disabling LCPLL · bd633a7c
      Paulo Zanoni 提交于
      This was causing WARNs in one machine, so instead of trying to guess
      exactly which hotplug bits should exist, just do the test on the
      non-HPD bits. We don't care about the state of the hotplug bits, we
      just care about the others, that need to be 1.
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@gmail.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      bd633a7c
    • P
      drm/i915: grab force_wake when restoring LCPLL · 215733fa
      Paulo Zanoni 提交于
      If LCPLL is disabled, there's a chance we might be in package C8 state
      or deeper, and we'll get a hard hang when restoring LCPLL (also, a red
      led lights up on my motherboard). So grab the force_wake, which will
      get us out of RC6 and, as a consequence, out of PC8+ (since we need
      RC6 to get into PC8+).
      
      Note: Discussions with hw designers are still ongoing what exactly
      goes boom here. But I think we can go ahead and just merge this little
      hack for now until it's clear what we actually need.
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      [danvet: Add small note about the current state of the discussion
      around this hack.]
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      215733fa
    • J
      drm/i915: drop WaMbcDriverBootEnable workaround · 3414caf6
      Jesse Barnes 提交于
      Turns out the BIOS will do this for us as needed, and if we try to do it
      again we risk hangs or other bad behavior.
      
      Note that this seems to break libva on ChromeOS after resumes (but
      strangely _not_ after booting up).
      
      This essentially reverts
      
      commit b4ae3f22
      Author: Jesse Barnes <jbarnes@virtuousgeek.org>
      Date:   Thu Jun 14 11:04:48 2012 -0700
      
          drm/i915: load boot context at driver init time
      
      and
      
      commit b3bf0766
      Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
      Date:   Tue Nov 20 13:27:44 2012 -0200
      
          drm/i915: implement WaMbcDriverBootEnable on Haswell
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      Reported-and-Tested-by: NStéphane Marchesin <marcheu@chromium.org>
      [danvet: Add note about impact and regression citation.]
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      3414caf6
    • R
      drm/i915: Cleaning up the relocate entry function · 5032d871
      Rafael Barbalho 提交于
      As the relocate entry function was getting a bit too big I've moved
      the code that used to use either the cpu or the gtt to for the
      relocation into two separate functions.
      Signed-off-by: NRafael Barbalho <rafael.barbalho@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      5032d871
    • P
      drm/i915: merge HSW and SNB PM irq handlers · 1403c0d4
      Paulo Zanoni 提交于
      Because hsw_pm_irq_handler does exactly what gen6_rps_irq_handler does
      and also processes the 2 additional VEBOX bits. So merge those
      functions and wrap the VEBOX bits on a HAS_VEBOX check. This
      check isn't really necessary since the bits are reserved on
      SNB/IVB/VLV, but it's a good documentation on who uses them.
      
      v2: - Change IS_HASWELL check to HAS_VEBOX
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      1403c0d4
    • P
      drm/i915: fix how we mask PMIMR when adding work to the queue · 4d3b3d5f
      Paulo Zanoni 提交于
      It seems we've been doing this ever since we started processing the
      RPS events on a work queue, on commit "drm/i915: move gen6 rps
      handling to workqueue", 4912d041.
      
      The problem is: when we add work to the queue, instead of just masking
      the bits we queued and leaving all the others on their current state,
      we mask the bits we queued and unmask all the others. This basically
      means we'll be unmasking a bunch of interrupts we're not going to
      process. And if you look at gen6_pm_rps_work, we unmask back only
      GEN6_PM_RPS_EVENTS, which means the bits we unmasked when adding work
      to the queue will remain unmasked after we process the queue.
      
      Notice that even though we unmask those unrelated interrupts, we never
      enable them on IER, so they don't fire our interrupt handler, they
      just stay there on IIR waiting to be cleared when something else
      triggers the interrupt handler.
      
      So this patch does what seems to make more sense: mask only the bits
      we add to the queue, without unmasking anything else, and so we'll
      unmask them after we process the queue.
      
      As a side effect we also have to remove that WARN, because it is not
      only making sure we don't mask useful interrupts, it is also making
      sure we do unmask useless interrupts! That piece of code should not be
      responsible for knowing which bits should be unmasked, so just don't
      assert anything, and trust that snb_disable_pm_irq should be doing the
      right thing.
      
      With i915.enable_pc8=1 I was getting ocasional "GEN6_PMIIR is not 0"
      error messages due to the fact that we unmask those unrelated
      interrupts but don't enable them.
      
      Note: if bugs start bisecting to this patch, then it probably means
      someone was relying on the fact that we unmask everything by accident,
      then we should fix gen5_gt_irq_postinstall or whoever needs the
      accidentally unmasked interrupts. Or maybe I was just wrong and we
      need to revert this patch :)
      
      Note: This started to be a more real issue with the addition of the
      VEBOX support since now we do enable more than just the minimal set of
      RPS interrupts in the IER register. Which means after the first rps
      interrupt has happened we will never mask the VEBOX user interrupts
      again and so will blow through cpu time needlessly when running video
      workloads.
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: NBen Widawsky <ben@bwidawsk.net>
      [danvet: Add note that this started to matter with VEBOX much more.]
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      4d3b3d5f
    • P
      drm/i915: don't queue PM events we won't process · 60611c13
      Paulo Zanoni 提交于
      On SNB/IVB/VLV we only call gen6_rps_irq_handler if one of the IIR
      bits set is part of GEN6_PM_RPS_EVENTS, but at gen6_rps_irq_handler we
      add all the enabled IIR bits to the work queue, not only the ones that
      are part of GEN6_PM_RPS_EVENTS. But then gen6_pm_rps_work only
      processes GEN6_PM_RPS_EVENTS, so it's useless to add anything that's
      not GEN6_PM_RPS_EVENTS to the work queue.
      
      As a bonus, gen6_rps_irq_handler looks more similar to
      hsw_pm_irq_handler, so we may be able to merge them in the future.
      
      v2: - Add a WARN in case we queued something we're not going to
            process.
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (v1)
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      60611c13
    • P
      drm/i915: don't disable/reenable IVB error interrupts when not needed · 333a8204
      Paulo Zanoni 提交于
      If the error interrupts are already disabled, don't disable and
      reenable them. This is going to be needed when we're in PC8+, where
      all the interrupts are disabled so we won't risk re-enabling
      DE_ERR_INT_IVB.
      
      v2: Use dev_priv->irq_mask (Chris)
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@gmail.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      333a8204
    • P
      drm/i915: add dev_priv->pm_irq_mask · 605cd25b
      Paulo Zanoni 提交于
      Just like irq_mask and gt_irq_mask, use it to track the status of
      GEN6_PMIMR so we don't need to read it again every time we call
      snb_update_pm_irq.
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@gmail.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      605cd25b
    • P
      drm/i915: don't update GEN6_PMIMR when it's not needed · f52ecbcf
      Paulo Zanoni 提交于
      I did some brief tests and the "new_val = pmimr" condition usually
      happens a few times after exiting games.
      
      Note: This is also prep work to track the GEN6_PMIMR register state in
      dev_priv->pm_imr. This happens in the next patch.
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@gmail.com>
      [danvet: Add note to explain why we want this, as per the discussion
      between Chris and Paulo.]
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      f52ecbcf
    • P
      drm/i915: wrap GEN6_PMIMR changes · edbfdb45
      Paulo Zanoni 提交于
      Just like we're doing with the other IMR changes.
      
      One of the functional changes is that not every caller was doing the
      POSTING_READ.
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@gmail.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      edbfdb45
    • P
      drm/i915: wrap GTIMR changes · 43eaea13
      Paulo Zanoni 提交于
      Just like the functions that touch DEIMR and SDEIMR, but for GTIMR.
      The new functions contain a POSTING_READ(GTIMR) which was not present
      at the 2 callers inside i915_irq.c.
      
      The implementation is based on ibx_display_interrupt_update.
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@gmail.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      43eaea13
    • P
      drm/i915: add the FCLK case to intel_ddi_get_cdclk_freq · a4006641
      Paulo Zanoni 提交于
      We already have code to disable LCPLL and switch to FCLK, so we need this too.
      We still don't call the code to disable LCPLL, but we'll call it when we add
      support for Package C8+.
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@gmail.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      a4006641
    • J
      drm/i915: Expose energy counter on SNB+ through debugfs · ec013e7f
      Jesse Barnes 提交于
      On SNB and IVB, there's an MSR (also exposed through MCHBAR) we can use
      to read out the amount of energy used over time.  Expose this in sysfs
      to make it easy to do power comparisons with different configurations.
      
      If the platform supports it, the file will show up under the
      drm/card0/power subdirectory of the PCI device in sysfs as gt_energy_uJ.
      The value in the file is a running total of energy (in microjoules)
      consumed by the graphics device.
      
      v2: move to sysfs (Ben, Daniel)
          expose a simple value (Chris)
          drop unrelated hunk (Ben)
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      
      v3: by Ben
      Tied it into existing rc6  sysfs entries and named that a more generic
      "power attrs." Fixed rebase conflicts.
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      
      v4: Since RAPL is a real driver that already exists to serve power
      monitoring, place our entry in debugfs. This gives me a fallback
      location for systems that do not expose it otherwise.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      ec013e7f
    • D
      drm/i915: Remove I915_READ_{NOPID, SYNC_0, SYNC_1})() · e3ce7633
      Damien Lespiau 提交于
      The code directly uses the registers and ring->mmio_base.
      Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      e3ce7633
    • D
      drm: Remove IS_IRONLAKE_D() · 3abdb334
      Damien Lespiau 提交于
      This define hasn't been used since:
      
        commit cfdf1fa2
        Author: Kristian Høgsberg <krh@bitplanet.net>
        Date:   Wed Dec 16 15:16:16 2009 -0500
      
            drm/i915: Implement IS_* macros using static tables
      Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      3abdb334
    • D
      drm/i915: Remove HAS_PIPE_CONTROL() · fdaa930b
      Damien Lespiau 提交于
      The code using this was removed in:
      
        commit 88f23b8f
        Author: Chris Wilson <chris@chris-wilson.co.uk>
        Date:   Sun Dec 5 15:08:31 2010 +0000
      
            drm/i915: Avoid using PIPE_CONTROL on Ironlake
      Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      fdaa930b
    • D
      drm/i915: Remove DSPARB_HWCONTROL() · 82548600
      Damien Lespiau 提交于
      This define hasn't been used since:
      
        commit 652c393a
        Author: Jesse Barnes <jbarnes@virtuousgeek.org>
        Date:   Mon Aug 17 13:31:43 2009 -0700
      
            drm/i915: add dynamic clock frequency control
      Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      82548600
    • J
      drm/i915: make IVB FDI training match spec v3 · 139ccd3f
      Jesse Barnes 提交于
      The existing code was trying different vswing and preemphasis settings
      in the wrong place, and wasn't trying them enough.  So add a loop to
      walk through them, properly disabling FDI TX and RX in between if a
      failure is detected.
      
      v2: remove unneeded reg writes, add delays around bit lock checks (Jesse)
      v3: fix TX and RX disable per spec (Paulo)
          fix delays per spec (Paulo)
          make RX symbol lock check match TX bit lock check (Paulo)
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51983Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      139ccd3f
    • B
      drm/i915/vma: Correct use after free in eviction · 8637b407
      Ben Widawsky 提交于
      The vma will [possibly] be destroyed during unbind in eviction.
      Immediately after this, we try to delete the list entry.
      
      Chris and Ville did the debug on this before I woke up, I just get to
      take credit for the fix :p
      
      For future reference the Oops that Mika reported:
      
      [  403.472448] BUG: unable to handle kernel paging request at 6b6b6b6b
      [  403.472473] IP: [<c12c1500>] __list_del_entry+0x20/0xe0
      [  403.472514] *pdpt = 000000002e89c001 *pde = 0000000000000000
      [  403.472556] Oops: 0000 [#1] SMP
      [  403.472582] Modules linked in: mxm_wmi snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_intel snd_hda_codec snd_hwdep snd_pcm snd_seq_midi snd_rawmidi psmouse snd_seq_midi_event snd_seq serio_raw snd_timer snd_seq_device snd soundcore snd_page_alloc wmi bnep rfcomm bluetooth mac_hid parport_pc ppdev lp parport usbhid dm_crypt firewire_ohci firewire_core crc_itu_t i915 drm_kms_helper e1000e ptp drm i2c_algo_bit pps_core xhci_hcd video
      [  403.472895] CPU: 2 PID: 1940 Comm: Xorg Not tainted 3.11.0-rc2+ #827
      [  403.472938] Hardware name:                  /DZ77BH-55K, BIOS BHZ7710H.86A.0070.2012.0416.2117 04/16/2012
      [  403.473002] task: ec866c00 ti: ee6a2000 task.ti: ee6a2000
      [  403.473039] EIP: 0060:[<c12c1500>] EFLAGS: 00013202 CPU: 2
      [  403.473078] EIP is at __list_del_entry+0x20/0xe0
      [  403.473109] EAX: f016d9bc EBX: f016d9bc ECX: 6b6b6b6b EDX: 6b6b6b6b
      [  403.473151] ESI: 00000000 EDI: ee6a3c90 EBP: ee6a3c60 ESP: ee6a3c48
      [  403.473193]  DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
      [  403.473230] CR0: 80050033 CR2: 6b6b6b6b CR3: 2ec43000 CR4: 001407f0
      [  403.473271] Stack:
      [  403.473285]  f63b2ff0 f61f98c0 f61f8000 f016d9bc 00000000 f016d9bc ee6a3cac f8519a4a
      [  403.473347]  00000000 00000000 10000000 f61f8000 0100a000 10000000 00000001 008ca000
      [  403.473410]  f64ee840 f61f98c0 f016d9bc f016dcec ee6a3c98 ee6a3c98 f61f98c0 dcc58f00
      [  403.473472] Call Trace:
      [  403.473509]  [<f8519a4a>] i915_gem_evict_something+0x17a/0x2d0 [i915]
      [  403.473567]  [<f8516ed1>] i915_gem_object_pin+0x271/0x660 [i915]
      [  403.473622]  [<f851c740>] ? i915_ggtt_clear_range+0x20/0x20 [i915]
      [  403.473676]  [<f8517afa>] i915_gem_object_pin_to_display_plane+0xda/0x190 [i915]
      [  403.473742]  [<f852d9fa>] intel_pin_and_fence_fb_obj+0xba/0x140 [i915]
      [  403.473800]  [<f852db40>] intel_gen7_queue_flip+0x30/0x1c0 [i915]
      [  403.473856]  [<f85337b0>] intel_crtc_page_flip+0x1a0/0x320 [i915]
      [  403.473911]  [<f847b549>] ? drm_framebuffer_reference+0x39/0x80 [drm]
      [  403.473965]  [<f847f9fb>] drm_mode_page_flip_ioctl+0x28b/0x320 [drm]
      [  403.474018]  [<f846fec8>] drm_ioctl+0x4b8/0x560 [drm]
      [  403.474064]  [<f847f770>] ? drm_mode_gamma_get_ioctl+0xd0/0xd0 [drm]
      [  403.474113]  [<c1140f8a>] ? do_sync_read+0x6a/0xa0
      [  403.474154]  [<f846fa10>] ? drm_copy_field+0x80/0x80 [drm]
      [  403.474193]  [<c115134c>] do_vfs_ioctl+0x7c/0x5b0
      [  403.474228]  [<c1141d2f>] ? vfs_read+0xef/0x160
      [  403.474263]  [<c108dcbb>] ? ktime_get_ts+0x4b/0x120
      [  403.474298]  [<c1151917>] SyS_ioctl+0x97/0xa0
      [  403.474330]  [<c1590bc1>] sysenter_do_call+0x12/0x22
      [  403.474364] Code: 55 f4 8b 45 f8 e9 75 ff ff ff 90 55 89 e5 53 83 ec 14 8b 08 8b 50 04 81 f9 00 01 10 00 74 24 81 fa 00 02 20 00 0f 84 8e 00 00 00 <8b> 1a 39 d8 75 62 8b 59 04 39 d8 75 35 89 51 04 89 0a 83 c4 14
      [  403.474566] EIP: [<c12c1500>] __list_del_entry+0x20/0xe0 SS:ESP 0068:ee6a3c48
      [  403.476513] CR2: 000000006b6b6b6b
      
      v2: Missed the drm_object_unreference use after free (Ville)
      Daniel Vetter <daniel@ffwll.ch> writes:
      Reported-by: NMika Kuoppala <mika.kuoppala@intel.com>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      [danvet: Add the Oops from Mika to the commit message.]
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      8637b407
  2. 22 8月, 2013 20 次提交