- 03 6月, 2020 1 次提交
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由 Kent Russell 提交于
Add the ReadSerial definitions for Arcturus to the arcturus_ppsmc.h header for use with unique_id Unrevert: Supported in SMU 54.23, update values to match SMU spec Signed-off-by: NKent Russell <kent.russell@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 30 5月, 2020 8 次提交
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由 Evan Quan 提交于
Thermal control is performed by PMFW. What handled in driver is just whether or not to enable the alert(to driver). Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
Also the new logics for MP1 SW IRQs disablement/enablement are added. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
Added missing thermal IRQs disablement on suspend. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
User can check and set the enablement of throttling logging and the interval between each logging. V2: simplify the sysfs interface(no string parsing) V3: add proper lock protection on updating throttling_logging_rs.interval V4: documentation cosmetic per Luben's suggestion Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NLuben Tuikov <luben.tuikov@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
Currently this feature is supported on Arcturus only. PMFW will interrupt driver the first time when thermal throttling happened and every one second afterwards if the throttling continuing. On receiving the 1st interrupt, driver logs it the first time. However, if the throttling continues, the logging will be performed every minute to avoid log flooding. V2: simplify the implemention by ratelimited printk Signed-off-by: NEvan Quan <evan.quan@amd.com> Acked-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
Enable this for Arcturus only for now. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
To fit the latest 54.24.0 PMFW. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NKenneth Feng <kenneth.feng@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
There will be no further interrupt without proper ack for current one. V2: fix typo to really set ACK bit only Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 29 5月, 2020 8 次提交
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由 Wenhui Sheng 提交于
smu_i2c_eeprom_init may be invoked twice or more under sroiv mode, while we don't want to add check if (!amdgpu_sriov_vf) before we invoke smu_i2c_eeprom_init/fini each time, so we check if i2c adapter is already added before we invoke i2c_add_adapter Signed-off-by: NWenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: NKevin Wang <kevin1.wang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Wenhui Sheng 提交于
We don't need SRIOV check after we enable SMC msg filter in SMU11 v2: squash in unused variable fix, unused ids Signed-off-by: NWenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: NKevin Wang <kevin1.wang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Wenhui Sheng 提交于
1. enable SMC message filter in SRIOV situation 2. return -EACCESS if msg is blocked from smu_msg_get_index 3. if msg is block, always return 0 from smu_v11_0_send_msg_with_param Signed-off-by: NWenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: NKevin Wang <kevin1.wang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Wenhui Sheng 提交于
1. add smu_11_0_msg_mapping definition 2. add valid info for each SMC message in SRIOV Signed-off-by: NWenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: NKevin Wang <kevin1.wang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
Since on early phase of bringup, the SMU IP may be not enabled or supported. Without this, we may hit null pointer dereference on accessing smu->adev. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NYong Zhao <Yong.Zhao@amd.com> Tested-by: NYong Zhao <Yong.Zhao@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Hua Zhang 提交于
When smu_i2c_eeprom_init is called on the smu resuming process under sroiv mode, there will be a call trace: [ 436.377690] dump_stack+0x63/0x85 [ 436.377695] kobject_init+0x77/0x90 [ 436.377704] device_initialize+0x28/0x110 [ 436.377708] device_register+0x12/0x20 [ 436.377756] i2c_register_adapter+0xeb/0x400 [ 436.377763] i2c_add_adapter+0x5a/0x80 [ 436.377951] arcturus_i2c_eeprom_control_init+0x60/0x80 [amdgpu] [ 436.378123] smu_resume+0xcc/0x110 [amdgpu] [ 436.378247] amdgpu_device_gpu_recover+0xfb1/0xfc0 [amdgpu] [ 436.378401] amdgpu_job_timedout+0xf2/0x150 [amdgpu] [ 436.378414] drm_sched_job_timedout+0x70/0xc0 [amd_sched] [ 436.378420] ? drm_sched_job_timedout+0x70/0xc0 [amd_sched] [ 436.378430] process_one_work+0x1fd/0x3f0 [ 436.378438] worker_thread+0x34/0x410 [ 436.378444] kthread+0x121/0x140 [ 436.378451] ? process_one_work+0x3f0/0x3f0 [ 436.378456] ? kthread_create_worker_on_cpu+0x70/0x70 [ 436.378464] ret_from_fork+0x35/0x40 This is because smu_i2c_eeprom is not released on gpu recovering. Actually, smu_i2c_eeprom_init/fini are only needed under bare mental mode. Signed-off-by: NHua Zhang <hua.zhang@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Kevin Wang 提交于
by default, vega20 will use legacy powerplay driver. in order to maintain the code conveniently in the future, remove the support of vega20 from swsmu. Signed-off-by: NKevin Wang <kevin1.wang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Kevin Wang 提交于
the vega20 asic uses legacy powerplay driver by default. 1. cleanup is_support_sw_smu_xgmi() function. (only use for vega20 xgmi pstate check) 2. by default, the vega20 set xgmi pstate by legacy powerplay routine. Signed-off-by: NKevin Wang <kevin1.wang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 23 5月, 2020 1 次提交
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由 Alex Deucher 提交于
Add some APU flags to simplify handling of different APU variants. It's easier to understand the special cases if we use names flags rather than checking device ids and silicon revisions. v2: rebase on latest code Acked-by: NEvan Quan <evan.quan@amd.com> Acked-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 22 5月, 2020 3 次提交
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由 Gustavo A. R. Silva 提交于
The current codebase makes use of one-element arrays in the following form: struct something { int length; u8 data[1]; }; struct something *instance; instance = kmalloc(sizeof(*instance) + size, GFP_KERNEL); instance->length = size; memcpy(instance->data, source, size); but the preferred mechanism to declare variable-length types such as these ones is a flexible array member[1][2], introduced in C99: struct foo { int stuff; struct boo array[]; }; By making use of the mechanism above, we will get a compiler warning in case the flexible array does not occur last in the structure, which will help us prevent some kind of undefined behavior bugs from being inadvertently introduced[3] to the codebase from now on. So, replace the one-element array with a flexible-array member. Also, make use of the new struct_size() helper to properly calculate the size of struct smu10_voltage_dependency_table. This issue was found with the help of Coccinelle and, audited and fixed _manually_. [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html [2] https://github.com/KSPP/linux/issues/21 [3] commit 76497732 ("cxgb3/l2t: Fix undefined behaviour") Acked-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NGustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
The prompts will contain pci address(segment/bus/port/function), severity(warn or error) and some keywords(GPU, amdgpu). Also this address the issue that pci bus retrieved by PCI_BUS_NUM(adev->pdev->devfn) is wrong. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 John Clements 提交于
during ras recovery block smu access via smi Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NJohn Clements <john.clements@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 15 5月, 2020 5 次提交
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由 John Clements 提交于
Updated SMC FW version check to determine if XGMI power down control is supported Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NJohn Clements <john.clements@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 John Clements 提交于
Added host to SMU FW cmd to enable/disable XGMI link power down Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NJohn Clements <john.clements@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
'ctxid' is used to distinguish different events raised from SMC. 0x3 and 0x4 are for AC and DC power mode. V2: update the way to retrieve the ctxid and change the log level to debug Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
To prevent further damage. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
Normally this(SW CTF) should not happen. And by doing graceful shutdown we can prevent further damage. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 12 5月, 2020 1 次提交
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由 Jane Jian 提交于
since for sriov, baco happens on host side, no need and meaning to judge is baco. also, since kiq reads strap0 in here, if kiq is not ready or gpu reset(kiq resume) happens after this read, would fail to read and wrongly set baco as true(1). Acked-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NJane Jian <Jane.Jian@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 09 5月, 2020 1 次提交
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由 Evan Quan 提交于
BACO is needed to support hibernate on Navi1X. Signed-off-by: NEvan Quan <evan.quan@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 07 5月, 2020 2 次提交
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由 ChenTao 提交于
Fixes warning because size is uint32_t and can never be negtative drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:1296:12: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] if (size < 0) Reported-by: NHulk Robot <hulkci@huawei.com> Signed-off-by: NChenTao <chentao107@huawei.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
Since gfxoff should be disabled first before trying to access those GC registers. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 01 5月, 2020 1 次提交
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由 Jason Yan 提交于
The struct member 'asic_setup' was assigned twice, let's remove one: static const struct pp_hwmgr_func smu10_hwmgr_funcs = { ...... .asic_setup = NULL, ...... .asic_setup = smu10_setup_asic_task, ...... }; This fixes the following coccicheck warning: drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c:1357:52-53: asic_setup: first occurrence line 1360, second occurrence line 1388 Signed-off-by: NJason Yan <yanaijie@huawei.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 28 4月, 2020 2 次提交
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由 Tiecheng Zhou 提交于
hwmgr->pm_en is initialized at hwmgr_hw_init. during amdgpu_device_init, there is amdgpu_asic_reset that calls to soc15_asic_reset (for V320 usecase, Vega10 asic), in which: 1) soc15_asic_reset_method calls to pp_get_asic_baco_capability (pm_en) 2) soc15_asic_baco_reset calls to pp_set_asic_baco_state (pm_en) pm_en is used in the above two cases while it has not yet been initialized So avoid using pm_en in the above two functions for V320 passthrough. Reviewed-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NTiecheng Zhou <Tiecheng.Zhou@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Tiecheng Zhou 提交于
This reverts commit c5207876. The commit being reverted changed the wrong place, it should have changed in func get_asic_baco_capability. Reviewed-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NTiecheng Zhou <Tiecheng.Zhou@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 24 4月, 2020 3 次提交
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由 Monk Liu 提交于
Signed-off-by: NMonk Liu <Monk.Liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Monk Liu 提交于
for ARCTURUS+ ASICS, we always support SW_SMU for bare-metal and for SRIOV one_vf_mode Signed-off-by: NMonk Liu <Monk.Liu@amd.com> Acked-by: NYintian Tao <yttao@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Monk Liu 提交于
Signed-off-by: NMonk Liu <Monk.Liu@amd.com> Acked-by: NYintian Tao <yttao@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 23 4月, 2020 4 次提交
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由 Jiansong Chen 提交于
Under onevf mode the smu support to other chips is not well verified yet. Signed-off-by: NJiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Prike Liang 提交于
Update the smu12_driver_if.h header to follow the pmfw release. Signed-off-by: NPrike Liang <Prike.Liang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Acked-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Yuxian Dai 提交于
for different ASIC support different the number of DPM levels, we should avoid to show the invalid level value. v1 -> v2: follow the suggestion,clarifiy the description for this change Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NYuxian Dai <Yuxian.Dai@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jason Yan 提交于
Fix the following gcc warning: drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/vega10_powertune.c:710:46: warning: ‘PSMGCEDCThresholdConfig_vega10’ defined but not used [-Wunused-const-variable=] static const struct vega10_didt_config_reg PSMGCEDCThresholdConfig_vega10[] = ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/vega10_powertune.c:654:46: warning: ‘PSMSEEDCThresholdConfig_Vega10’ defined but not used [-Wunused-const-variable=] static const struct vega10_didt_config_reg PSMSEEDCThresholdConfig_Vega10[] = ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Reported-by: NHulk Robot <hulkci@huawei.com> Signed-off-by: NJason Yan <yanaijie@huawei.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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