This file is not modular, nor is it using modular functions. The
only thing close is the global THIS_MODULE which comes from export.h
so lets replace it appropriately and cut back on the amount of
header stuff we draw in by several thousand lines.

Cc: linux-gpio@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The pxa2xxx fails some automated builds because of unexported
symbols.
Reported-by: Nkbuild test robot <fengguang.wu@intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

While I was testing irq's on the cubietruck I found a couple of
not working irq pins. Further diving into the problem it opened
up a mess called "manual".

This so called manual (A20 user manual v1.3 dated 2014-10-10) says:

Pin overview:
    Page 237:       EINT26 is on mux 5.
    Page 288:       EINT26 is on mux 6.

The manual is so contradicting that further tests had to be made
to see which of the 2 statements where correct.

This patch is based on actual outcome of these tests and not what
the manual says.

Test procedure used:

Connect a 1 pulse per second (GPS) line to the pin.

echo pin### > /sys/class/gpio/export
echo in > /sys/class/gpio/gpio###/direction
echo rising > /sys/class/gpio/gpio###/edge

Check /proc/interrupts if a irq was attached and if irq's where
received.

Hardware used:
Henry Paulissen: Cubietruck
Andere Przywara: BananaPi M1
Tested-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NAndre Przywara <andre.przywara@arm.com>
Signed-off-by: NHenry Paulissen <henry@nitronetworks.nl>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

While I was testing irq's on the cubietruck I found a couple of
not working irq pins. Further diving into the problem it opened
up a mess called "manual".

This so called manual (A20 user manual v1.3 dated 2014-10-10) says:

Pin overview:
    Page 233:       EINT12 is on pin PC19 mux6.
    Page 236:       EINT12 is on pin PH12 mux6.

Now, it is a bit strange to have the same IRQ on 2 different pins,
but I guess this could still be possible hardware wise. But then:

Pin registers:
    Page 253:       EINT12 is *not* on pin PC19.
    Page 281:       EINT12 is on pin PH12.

The manual is so contradicting that further tests had to be made
to see which of the 2 statements where correct.

This patch is based on actual outcome of these tests and not what
the manual says.

Test procedure used:

Connect a 1 pulse per second (GPS) line to the pin.

echo pin### > /sys/class/gpio/export
echo in > /sys/class/gpio/gpio###/direction
echo rising > /sys/class/gpio/gpio###/edge

Check /proc/interrupts if a irq was attached and if irq's where
received.
Signed-off-by: NHenry Paulissen <henry@nitronetworks.nl>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Commit bdb0066d ("mfd: syscon: Decouple syscon interface from platform
devices") added the possibility to register syscon devices without
associated platform device. This also removed regmap debugfs facilities,
which don't work without a device. This patch associates the syscon regmap
that handles the IOMUX controller's general purpose registers with the
pinctrl device so that the GPR registers appear in the regmap debugfs
directory again. For example, on i.MX6Q the GPR registers now can be
read from /sys/kernel/debug/regmap/20e0000.iomuxc-gpr/registers.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The DT bindings for pinctrl-bcm2835 allow both the function and pull
to contain either one entry or one per pin. However, an error in the
DT parsing can cause failures if the number of pulls differs from the
number of functions.

Cc: stable@vger.kernel.org
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NPhil Elwell <phil@raspberrypi.org>
Reviewed-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add support for setting up GPIO pin interrupts in the lpc18xx pinctrl
driver. The LPC18xx SCU contain two registers that sets up the signal
routing to the GPIO pin interrupt (PINT) block. The routing uses the
GPIO namespace and not the pin namespace so a lookup is preformed on
the pin.

Routing configuration is done in the device tree by using the new
nxp,gpio-pin-interrupt property. This property takes single parameter
which sets the PINT hwirq for the GPIO.
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

pinctrl_find_gpio_range_from_pin takes the pctldev->mutex but so
does pinconf_pins_show and this will cause a deadlock if
pinctrl_find_gpio_range_from_pin is used in .pin_config_get
callback.

Create a nolock version of pinctrl_find_gpio_range_from_pin to
allow pin to gpio lookup to be used from pinconf_pins_show.
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The initialization of ngroups is occurring at the end of the
first iteration of the outer loop, which means that the
assignment  pins[ngroups++] = i is potentially indexing into
a region outside of array pins because ngroups is not initialized.
Instead, initialize ngroups in the inner loop before the first
inner loop iteration.
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Reviewed-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds CANFD[0-1] pinmux support to r8a7795 SoC.
Signed-off-by: NRamesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds CAN[0-1] pinmux support to r8a7795 SoC.
Signed-off-by: NRamesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

GP2[29] muxing is controlled by 2-bit IP6[3:2] field, yet only 3 values
are listed instead of 4...

[Sergei: fixed up the formatting, renamed, added the changelog.]
Signed-off-by: NAndrey Gusakov <andrey.gusakov@cogentembedded.com>
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Make use of ARCH_RENESAS in place of ARCH_SHMOBILE.

This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This is set by the device core.

Cc: John Crispin <blogic@openwrt.org>
Reported-by: Nkbuild test robot <fengguang.wu@intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add the driver and header files required to make pinctrl work on MediaTek
MT7623.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

To use pin as eint, user should make sure that:
1. pin is set to right mode, this is done in .irq_request_resources
implementation already.
2. direction of the pin is input, which should call GPIO API to set
pin to input gpio.
We add what step 2 do to .irq_request_resources so that user doesn't
need call GPIO API any more when pin for eint usage.
Signed-off-by: NBiao Huang <biao.huang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Since input-disable cuts off input signal of gpio, add input-enable
setting in .gpio_request_enable implementation to ensure gpio function well
Signed-off-by: NBiao Huang <biao.huang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add the EtherAVB pin groups to the R8A7794 PFC driver.

Based on the patches by Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com>.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

The sh-pfc pinctrl driver is currently handling SoC-specific
PFC hardware blocks on ARM64, ARM and SH architectures.

For older SoCs using SH cores and some 32-bit ARM SoCs the PFC
hardware also provides GPIO functionality. On the majority of
32-bit ARM SoCs from Renesas and so far all ARM64 SoCs the GPIO
feature is provided by separate hardware blocks.

So far GPIO support in the PFC driver has been compiled-in for
the majority of the SoCs, but with this patch applied the SoCs
with PFC support may select from one of the following:
 - CONFIG_PINCTRL_SH_PFC - Used if PFC lacks GPIO hardware
 - CONFIG_PINCTRL_SH_PFC_GPIO - Used if PFC includes GPIO support

This patch results in the following changes:
 - The GPIO functionality is only compiled-in on relevant SoCs
 - The number of lines of code is reduced

Build tested using the following configurations:
 - r8a7795 -> CONFIG_PINCTRL_SH_PFC_GPIO=n -> OK (ARM64)
 - r8a7790 -> CONFIG_PINCTRL_SH_PFC_GPIO=n -> OK (ARM)
 - r8a7790 + r8a7740 -> CONFIG_PINCTRL_SH_PFC_GPIO=y -> OK (ARM)
 - r8a7740 -> CONFIG_PINCTRL_SH_PFC_GPIO=y -> OK (ARM)
 - sh7751 -> CONFIG_PINCTRL_SH_PFC=n -> OK (SH rts7751r2d1)
 - sh7724 -> CONFIG_PINCTRL_SH_PFC_GPIO=y -> OK (SH ecovec24)
Signed-off-by: NMagnus Damm <damm+renesas@opensource.se>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
[geert: s/def_bool n/bool/]
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds PWM[0-6] pinmux support to r8a7795 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
[uli: adapted to mainline PFC driver]
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Most pins on the r8a7795 SoC can be configured in GPIO mode for
interrupt and GPIO functionality, while a couple of them can also
be routed to the INTC-EX hardware block (formerly known as IRQC).

On r8a7795 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and
this patch adds support for them to the PFC driver as "intc_ex_irqN".

Tested on r8a7795 Salvator-X with an external loop back adapter on
EXIO_D that connects pin 9 (IRQ2/GP2_02) and pin 26 (ExA22/GP2_06).
Signed-off-by: NMagnus Damm <damm+renesas@opensource.se>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add the audio clock pin groups to the R8A7794 PFC driver.

[Sergei:  fixed pin group names to reflect the reality, fixed pin names in
the comments to *_pins[], lowercased the separator comment, resolved rejects,
added the changelog, renamed the patch.]
Signed-off-by: NRyo Kataoka <ryo.kataoka.wt@renesas.com>
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add the SSI pin groups to the R8A7794 PFC driver.

[Sergei: fixed inconsistent alternate pin group naming, split SSI5/6 pin
groups into data/control ones, moved SSI7 data B group to its proper place,
fixed  pin names in  the comments to *_pins[], extended Cogent Embedded's
copyright, added the changelog, renamed the patch.]
Signed-off-by: NRyo Kataoka <ryo.kataoka.wt@renesas.com>
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

The device core will handle this and Coccinelle complains.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add pinctrl driver support for IPQ4019 platform
Signed-off-by: NSricharan R <sricharan@codeaurora.org>
Signed-off-by: NMathieu Olivari <mathieu@codeaurora.org>
Signed-off-by: NVaradarajan Narayanan <varada@codeaurora.org>
Signed-off-by: NMatthew McClintock <mmcclint@codeaurora.org>
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NAndy Gross <andy.gross@linaro.org>
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
[Dropped .owner assignment]
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The function can return negative values, so its result should
be assigned to signed variable.

The problem has been detected using coccinelle semantic patch
scripts/coccinelle/tests/assign_signed_to_unsigned.cocci.

Fixes: 59ee9c96 ('pinctrl: mediatek: Add gpio_request_enable support')
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Acked-by: NHongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The pinctrl-amd driver builds just fine as a module so give
users this option.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Clang correctly points out that the section attribute for u300_gpio_confdata
is in the wrong place:

drivers/pinctrl/pinctrl-coh901.c:130:37: error: '__section__' attribute only applies to functions and global variables

This moves it from the type name to the variable, so it actually gets
discarded.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

In case of error, the function devm_ioremap_nocache() returns NULL
pointer not ERR_PTR(). The IS_ERR() test in the return value check
should be replaced with NULL test.
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Due to a typo Zynq pin controller does not set pin function of qspi1
when using function qspi1. So pin group for qspi1 has to be renamed to
"qspi1_0_grp" as outlined in the corresponding bindings documentation.

This also removes kernel message:
  zynq-pinctrl 700.pinctrl: invalid group "qspi1_0_grp" for function "qspi1"
Signed-off-by: NHelmut Buchsbaum <helmut.buchsbaum@gmail.com>
Acked-by: NSören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

CONFIG_PINCTRL_MTK is more suitable than CONFIG_ARCH_MEDIATEK
to guard the drivers/pinctrl/mediatek/ directory.
(I renamed CONFIG_PINCTRL_MTK_COMMON to CONFIG_PINCTRL_MTK.)

This allows COMPILE_TEST to descend into drivers/pinctrl/mediatek
without CONFIG_ARCH_MEDIATEK define.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

pinctrl-intel doesn't use anything from <linux/init.h>,
<linux/acpi.h>, <linux/gpio.h> or <linux/pm.h>, so it should not
include these header files.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

sunxi_pmx_set accepts pin number and then calculates offset by
subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
gets offset so we have to convert it to pin number so we won't get
negative value in sunxi_pmx_set.

This was only used on A10 so far, where there is only one GPIO chip with
pin_base set to 0 so it didn't matter. However H3 also requires this
workaround but have two pinmux sections, triggering problem for PL port.
Signed-off-by: NKrzysztof Adamski <k@japko.eu>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

H3 has additional PIO controller similar to what we can find on A23.
It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.
Signed-off-by: NKrzysztof Adamski <k@japko.eu>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The pinctrl of rk3399 is much different from other's,
especially the 3bits of drive strength.
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add COMPILE_TEST for the compilation test coverage.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

While selecting the driver for compile testing seemed possible,
the driver was not compiled because the driver directory was only
added if ARCH_STM32 was selected.

This patch now makes the pinctrl Makefile to add stm32 directory if
PINCTRL_STM32 is selected.
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Some macros where defined in DT bindings headers, whereas only used
in the driver.

This patch moves these macros to the driver side.
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds USB[0-2] (USB2.0 host) pinmux support to r8a7795 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Cfr. Manual Errata for Rev 0.50 of the R-Car Gen3 datasheet.

This has no user-visible impact, as the definitions were not really
used.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>