This iomux is called iomux-v3 in the tree because it is the third known
incarnation of MXC iomuxers. It is not only found on the MX35 but also
on the MX51 and probably others.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

The i.MX31 ARM11 core is not a v6K core. Disable this option as it
is incompatible with non v6K cores.
Signed-off-by: NMagnus Lilja <lilja.magnus@gmail.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Before this patch I got the following line in my dmesg:

	[    0.000000] BUG: mapping for 0xd4000000 at 0xeb000000 overlaps vmalloc space

VMALLOC_END is 0xf4000000 and there are the following other mappings
defined for mx27ads:

	(0xa0500000,+0x00001000) maps to 0xffff0000
	(0x10000000,+0x00100000) maps to 0xf4000000
	(0x80000000,+0x00100000) maps to 0xf4100000
	(0xd8000000,+0x00100000) maps to 0xf4200000

So map PBC to 0xf4300000.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

On i.MX31 I sometimes get spurious interrupts. There is no need
to crash the whole system when this happens. Instead, silently
ignore it.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

We want to have a mx31_defconfig file that builds a kernel that is able
to boot on all support mx31 systems and thus also can be better tested
by automatic build scripts. For these reasons, this config file is not
needed anymore.
Signed-off-by: NValentin Longchamp <valentin.longchamp@epfl.ch>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

All i.MX platforms support <linux/clk.h> calls and should select HAVE_CLK.
Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

On MX2 platforms imx_dma_request() calls request_irq() which may sleep
with interrupts disabled.
Signed-off-by: NMartin Fuzzey <mfuzzey@gmail.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

The sequence
	imx_dma_request()
	imx_dma_enable()
	imx_dma_free()
left the dma channel in_use mode and did not release the timer.
Signed-off-by: NMartin Fuzzey <mfuzzey@gmail.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

This patch is a workaround for the 460075 Cortex-A8 (r2p0) erratum. It
configures the L2 cache auxiliary control register so that the Write
Allocate mode for the L2 cache is disabled.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch adds a workaround for the 458693 Cortex-A8 (r2p0)
erratum. It sets the corresponding bits in the auxiliary control
register so that the PLD instruction becomes a NOP.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch adds the workaround for the 430973 Cortex-A8 (r1p0..r1p2)
erratum. The BTAC/BTB is now flushed at every context switch.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch implements the recommended workaround for erratum 411920
(ARM1136, ARM1156, ARM1176).
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

arm is placing some code in the .text.init section, but it does not
reference that section in its linker scripts.

This change moves this code from the .text.init section to the
.init.text section, which is presumably where it belongs.
Signed-off-by: NTim Abbott <tabbott@mit.edu>
Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Acked-by: NSam Ravnborg <sam@ravnborg.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Update NAND partitioning for the dm6446 evm, unmasking the hidden
data at the beginning and letting the kernel be updated from Linux.

 - This is boot-compatible with TI's software (U-Boot 1.20 and both
   the 2.6.10 and 2.6.18 kernels), in terms of startup and loading
   kernels from flash.

 - In the same way, it's also boot-compatible with mainline U-Boot,
   which stores U-Boot params in block 0 not block 16.

 - It's not quite compatible with systems that previously used NAND
   partitions to hold (filesystem) data.  The compatibilities are a
   bit different based on which kernel was used previously
     + Users of TI/MV kernels no longer see mtd2 "params"
       (mainline u-boot env is in a different place)
	* Filesystem is now mtd2 ... vs mtd3
     + Users of GIT kernels now see mtd0 and mtd1 partitions
	* Filesystem partition starts 640 KBytes earlier
	* Filesystem is now mtd2 ... vs mtd0
     * Linux now *uses* the flash-resident BBT
	* Removes annoying slowdown/hiccup during boot
	* Potentially ~64KB less space available with TI/MV kernels

If you *used* NAND partitions from Linux, there is no solution that's
fully compatible with all previous kernels in those respects ... ergo
this "best compromise".  It'd be good to back back up the filesystem
data; or, carry your own backwards-compatibility patch for awhile.
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Rework DM644x code into SoC specific and board specific parts.
This is also to generalize the structure a bit so it's easier to add
support for new SoCs in the DaVinci family.
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Rename DM6446 EVM board file, no functional changes.  Code is updated
and reworked in following patch.
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Update MUX support to be more general and useful across multiple
SoCs in the DaVinci family.
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Adding IRQ defintions for DaVinci DM355 and default interrupt
priorities for DM355
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Clear any set bits in the 'NEXT' field of the MDCTL register in the
Power and Sleep Controller (PSC) before setting any new bits.
This also allows some minor cleanup by removing some no longer
needed lines of code.
Signed-off-by: NMark A. Greer <mgreer@mvista.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Update the DaVinci GPIO code to work better on non-dm6446 parts,
notably the dm355:

 - Only handle the number of GPIOs the chip actually has.  So
   for example on dm6467, GPIO-42 is the last GPIO, and trying
   to use GPIO-43 now fails cleanly; or GPIO-72 on dm6446.

 - Enable GPIO interrupts on each 16-bit GPIO-irq bank ...
   previously, only the first five were enabled, so GPIO-80
   and above (on dm355) wouldn't trigger IRQs.

 - Use the right IRQ for each GPIO bank.  The wrong values were
   used for dm355 chips, so GPIO IRQs got routed incorrectly.

 - Handle up to four pairs of 16-bit GPIO banks ... previously
   only three were handled, so accessing GPIO-96 and up (e.g. on
   dm355) would oops.

 - Update several comments that were dm6446-specific.

Verified by receiving GPIO-1 (dm9000) and GPIO-5 (msp430) IRQs
on the DM355 EVM.

One thing this doesn't do is handle the way some of the GPIO
numbers on dm6467 are reserved but aren't valid as GPIOs.  Some
bitmap logic could fix that if needed.
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Original code for 2.6.10 and 2.6.28 series done by Texas Instruments
and MontaVista, but major updates and rework done by Troy Kisky and
David Brownell.

Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Use clock framework instead of hard-coded CLOCK_TICK_RATE for
determining timer tick frequencies.
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Signed-off-by: NEric Miao <eric.miao@marvell.com>

Signed-off-by: NEric Miao <eric.miao@marvell.com>

GPIO17_SDATA_IN_1 and GPIO36_SDATA_IN_1 are originally designed for the 2nd
codec but unused on the board, yet they are initialized incorrectly by the
bootloader as the SDATA_IN_1 alternate function, thus causing AC97 fail to
work. Fix this issue by configuring these pins as normal GPIO to avoid the
noise from these pins being treated as signals from the 2nd codec.
Signed-off-by: NEric Miao <eric.miao@marvell.com>

Signed-off-by: NEric Miao <eric.miao@marvell.com>

cpufreq drivers for pxa2xx/3xx are now built-in automatically as soon as
CPU_FREQ is enabled.
Signed-off-by: NPhilipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: NEric Miao <eric.miao@marvell.com>

ARCH_PXA selects HAVE_CLK and COMMON_CLKDEV twice in arch/arm/Kconfig.
Remove the second entry.
Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NEric Miao <eric.miao@marvell.com>

pxa_gpio_irq_type() and pxa_unmask_muxed_gpio() will touch non-muxed GPIOs
(0 and 1 on PXA2xx/PXA3xx) bits in GRERx and GFERx, which is incorrect.
Actually, only those bits should get updated if the corresponding bits are
set in c->irq_mask as well. Fix this by updating only those relevant bits.
Reported-and-tested-by: NDaniel Ribeiro <drwyrm@gmail.com>
Signed-off-by: NEric Miao <eric.miao@marvell.com>

arch/arm/mach-sa1100/lart.c:36: error: 'PAGE_SHIFT' undeclared here (not in a function)
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Add a function omap2_gp_clockevent_set_gptimer() for board-*.c files
to use in .init_irq functions to configure the system tick GPTIMER.
Practical choices at this point are GPTIMER1 or GPTIMER12.  Both of
these timers are in the WKUP powerdomain, and so are unaffected by
chip power management.  GPTIMER1 can use sys_clk as a source, for
applications where a high-resolution timer is more important than
power management.  GPTIMER12 has the special property that it has the
secure 32kHz oscillator as its source clock, which may be less prone
to glitches than the off-chip 32kHz oscillator.  But on HS devices, it
may not be available for Linux use.

It appears that most boards are fine with GPTIMER1, but BeagleBoard
should use GPTIMER12 when using a 32KiHz timer source, due to hardware bugs
in revisions B4 and below.  Modify board-omap3beagle.c to use GPTIMER12.

This patch originally used a Kbuild config option to select the GPTIMER,
but was changed to allow this to be specified in board-*.c files, per
Tony's request.

Kalle Vallo <kalle.valo@nokia.com> found a bug in an earlier version of
this patch - thanks Kalle.

Tested on Beagle rev B4 ES2.1, with and without CONFIG_OMAP_32K_TIMER, and
3430SDP.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Cc: Kalle Valo <kalle.valo@nokia.com>

All GP timers on OMAP2/3 can generate wakeup events.  The wakeup status is
cleared in the PRCM interrupt handler.
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

GPTIMER12 IRQ is at IRQ 95 on OMAP3, unlike OMAP2.  (ref: OMAP34xx
Multimedia High Security (HS) Device Silicon Revision 3.0 Security
Addendum Rev. B, SWPU119B)
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Typo error when requesting for clock for dsp in omap1
Signed-off-by: NArun KS <arunks@mistralsolutions.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

This patch avoids waiting for the camera module to become ready,
since it doesn't have IDLEST bit.

Based on a earlier hack done by Paul Walmsley on Sep 9 2008 on
linux-omap tree.
Signed-off-by: NSergio Aguirre <saaguirre@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Commit 8ad8ff65 breaks the OMAP2xxx
cpu_mask code, which causes OMAP2xxx to panic on boot.  Fix by
removing the cpu_mask auto variable and by changing CK_242X
and CK_243X to use RATE_IN_242X/RATE_IN_243X.

Resolves

<1>Unable to handle kernel NULL pointer dereference at virtual address 0000000c
<1>pgd = c0004000
<1>[0000000c] *pgd=00000000
Internal error: Oops: 5 [#1]
Modules linked in:
CPU: 0    Not tainted  (2.6.29-omap1 #32)
PC is at omap2_clk_set_parent+0x104/0x120
LR is at omap2_clk_set_parent+0x28/0x120
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Tested-by: NJarkko Nikula <jarkko.nikula@nokia.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>

Symbols like SOFT_RESET are way too generic to be exported at large.
To avoid this, let's move the mbus bridge register defines into a
separate file and include it where needed.  This affects mach-kirkwood,
mach-loki, mach-mv78xx0 and mach-orion5x simultaneously as they all
share code in plat-orion which relies on those defines.

Some other defines have been moved to narrower scopes, or simply deleted
when they had no user.

This fixes compilation problem with mpt2sas on the above listed
platforms.
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>