1. 18 6月, 2015 1 次提交
  2. 16 6月, 2015 1 次提交
    • C
      spi: atmel: add support to FIFOs · 11f2764f
      Cyrille Pitchen 提交于
      The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
      When FIFOs are enabled, they can either work in SINGLE data mode or
      MULTIPLE data mode. The selected mode depends on the configuration of the
      SPI controller (see below).
      
      In SINGLE data mode (or legacy mode), for a single I/O access, only one
      data can be read from the Receive Data Register (RDR) or written into the
      Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
      to 4 data can be read from the RDR or up 2 data can be written into the
      TDR in a single 32bit I/O access. So programmers should take good care of
      the width of the I/O access to read/write the right number of data. The
      exact number of read/written data depends on both the I/O access width and
      the data width (from 8 up to 16 bits).
      
      To enable the FIFO feature a "atmel,fifo-size" property must be set to
      provide the maximum number of data (not bytes) the RX and TX FIFOs can
      store. Hence a 32 data FIFO can always store up to 32 data unrelated with
      the actual data width.
      
      When FIFOs are enabled, the RX one is forced to operate in SINGLE data
      mode because this driver configures the spi controller as a master. In
      master mode only, the Received Data Register has an additionnal Peripheral
      Chip Select field, which prevents us from reading more than a single data
      at each register access.
      
      Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
      8bit data size is used, only two data by access could be written into the
      Transmit Data Register. Indeed the first data has to be written into the
      lowest 16 bits whereas the second data has to be written into the highest
      16 bits of the TDR. When DMA transfers are used to send data, we don't
      rework the transmit buffer to cope with this hardware limitation: the
      additional copies required to prepare a new input buffer suited to both
      the DMA controller and the spi controller would waste all the benefit of
      the DMA transfer. Instead, the DMA controller is configured to write only
      one data at time into the TDR.
      
      In pio mode, two data are written in the TDR in a single access.
      Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
      Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      11f2764f
  3. 15 6月, 2015 1 次提交
  4. 13 6月, 2015 2 次提交
  5. 11 6月, 2015 1 次提交
  6. 10 6月, 2015 3 次提交
    • H
      spi: spi-fsl-dspi: Change the way of increasing spi_message->actual_length · c042af95
      Haikun Wang 提交于
      In current driver, we increase actual_length in the following way:
      message->actual_length += dspi_xxx_transfer()
      It has two defects.
      First, transmitting maybe in process when the function call finished and
      we don't know the transmitting result in this moment.
      Secondly, the last sentence in function before returning is accessing the
      SPI register and trigger the data transmitting. If we enable interrupt,
      interrupt may be generated before function return and we also have the same
      sentence "message->actual_length += dspi_xxx_transfer()"
      in the IRQ handler.
      And usually dspi_xxx_transfer will trigger a new IRQ.
      The original dspi_xxx_transfer call may return when no new IRQ generate.
      This may mess the variable spi_message->actual_length.
      Now we increase the variable in the IRQ handler and only when we get the
      TCF or EOQ interrupt
      And we get the transmitted data length from the SPI transfer counter
      instead of the function return value.
      Signed-off-by: NHaikun Wang <haikun.wang@freescale.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      c042af95
    • H
      spi: spi-fsl-dspi: Enable TCF interrupt mode support · d1f4a38c
      Haikun Wang 提交于
      DSPI module has two optional interrupts when complete data transfer.
      One is EOQ interrupt, the other one is TCF interrupt.
      EOQ indicates a queue of data frame has been transmitted.
      TCF indicates a frame has been transmitted.
      This patch enable support TCF mode.
      Driver binds a correct interrupt mode to every compatible string.
      User should use the correct compatible string in the dts node.
      Signed-off-by: NHaikun Wang <haikun.wang@freescale.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      d1f4a38c
    • C
      spi: atmel: add support for the internal chip-select of the spi controller · 48203034
      Cyrille Pitchen 提交于
      This patch relies on the CSAAT (Chip Select Active After Transfer) feature
      introduced by the version 2 of the spi controller. This new mode allows to
      use properly the internal chip-select output pin of the spi controller
      instead of using external gpios. Consequently, the "cs-gpios" device-tree
      property becomes optional.
      
      When the new CSAAT bit is set into the Chip Select Register, the internal
      chip-select output pin remains asserted till both the following conditions
      become true:
      - the LASTXFER bit is set into the Control Register (or the Transmit Data
        Register)
      - the Transmit Data Register and its shift register are empty.
      
      WARNING: if the LASTXFER bit is set into the Control Register then new
      data are written into the Transmit Data Register fast enough to keep its
      shifter not empty, the chip-select output pin remains asserted. Only when
      the shifter becomes empty, the chip-select output pin is unasserted.
      
      When the CSAAT bit is clear in the Chip Select Register, the LASTXFER bit
      is ignored in both the Control Register and the Transmit Data Register.
      The internal chip-select output pin remains active as long as the Transmit
      Data Register or its shift register are not empty.
      Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
      Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      48203034
  7. 09 6月, 2015 1 次提交
  8. 05 6月, 2015 3 次提交
  9. 03 6月, 2015 1 次提交
    • M
      spi: restore rx/tx_buf in case of unset CONFIG_HAS_DMA · 4b786458
      Martin Sperl 提交于
      The case where spi_master sets the flags SPI_MASTER_MUST_RX/TX while
      CONFIG_HAS_DMA is unset (which is unlikley) together with a driver
      that reuses spi_messages with rx/tx_buff set to NULL, can result in:
      * data disclosure over the SPI (for tx_buf == NULL)
      * memory corruption (for rx_buf == NULL)
      
      This happenes when dummy_rx/dummy_tx are changing address due to krealloc
      or free and an allocation of the memory by a different part of the kernel.
      Signed-off-by: NMartin Sperl <kernel@martin.sperl.org>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      4b786458
  10. 02 6月, 2015 2 次提交
  11. 28 5月, 2015 1 次提交
    • G
      spi: orion: Fix extended baud rates for each Armada SoCs · 4dacccfa
      Gregory CLEMENT 提交于
      The commit df59fa7f "spi: orion: support armada extended baud
      rates" made the assumptions that all the Armada SoCs supported the
      same maximum frequency. However, according the hardware datasheet, the
      maximum frequency supported by the Armada 370 SoC is tclk/4, for the
      Armada XP, Armada 38x and Armada 39x SoCs the limitation is 50MHz and
      for the Armada 375 it is tclk/15.
      
      This patch introduces new compatible strings to handle all these
      case. In order to be future proof a compatible was created for each
      SoC even if currently some SoCs seem using the same IP.
      Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      4dacccfa
  12. 26 5月, 2015 3 次提交
  13. 25 5月, 2015 4 次提交
  14. 22 5月, 2015 2 次提交
    • J
      spi: fsl-espi: Fix an error that can cause fsl espi task blocked · 7a0a1759
      Jane Wan 提交于
      Incorrect condition is used in spin_event_timeout().  When the TX is
      done, the SPIE_NF bit in ESPI_SPIE register is set to 1 to indicate the
      Tx FIFO is not full.  If the bit is 0, it indicates the Tx FIFO is full.
      
      Due to this error, if the Tx FIFO is full at the beginning, but becomes
      not full after handling the Rx FIFO (the SPIE_NF bit is set), the
      spin_event_timeout() returns with timeout occurred.  It causes the
      interrupt handler not to send completion notification to the thread that
      called wait_for_complete() waiting for the notification.
      Signed-off-by: NJane Wan <Jane.Wan@gainspeed.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      7a0a1759
    • H
      spi: spi-fsl-dspi: Bug fix incorrect CS de-assert · 9deef024
      Haikun Wang 提交于
      SPI chip select signal need to keep asserted between several
      spi_transfer in the same spi_message usually.
      But the driver will de-assert CS signal and the assert it between
      serval spi_transfer in the same spi_message under some condiations.
      This patch fix the bug.
      
      Here is an example:
      Assume you have two variables like the following,
      struct spi_transfer a;
      struct spi_transfer b;
      if you send a spi_message only includes 'a' first,
      and then you send a spi_message includes 'a' and 'b'
      but without resetting 'a'.
      Driver will de-assert CS and then assert CS between 'a' and 'b'.
      Signed-off-by: NHaikun Wang <haikun.wang@freescale.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      9deef024
  15. 21 5月, 2015 1 次提交
  16. 13 5月, 2015 1 次提交
  17. 12 5月, 2015 4 次提交
  18. 11 5月, 2015 1 次提交
  19. 09 5月, 2015 1 次提交
  20. 08 5月, 2015 1 次提交
  21. 07 5月, 2015 3 次提交
  22. 06 5月, 2015 1 次提交
  23. 04 5月, 2015 1 次提交
    • Y
      spi: bcm2835: depends GPIOLIB · e0d58cdc
      Yoshinori Sato 提交于
      I got following error on CONFIG_GPIOLIB=n.
      
      drivers/spi/spi-bcm2835.c: In function 'chip_match_name':
      drivers/spi/spi-bcm2835.c:356:21: error: dereferencing pointer to incomplete type 'struct gpio_chip'
        return !strcmp(chip->label, data);
                           ^
      drivers/spi/spi-bcm2835.c: In function 'bcm2835_spi_setup':
      drivers/spi/spi-bcm2835.c:382:9: error: implicit declaration of function 'gpiochip_find' [-Werror=implicit-function-declaration]
        chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
               ^
      drivers/spi/spi-bcm2835.c:382:7: warning: assignment makes pointer from integer without a cast [-Wint-conversion]
        chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
             ^
      drivers/spi/spi-bcm2835.c: In function 'chip_match_name':
      drivers/spi/spi-bcm2835.c:357:1: warning: control reaches end of non-void function [-Wreturn-type]
       }
       ^
      Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      e0d58cdc