- 18 6月, 2015 1 次提交
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由 Mark Brown 提交于
Signed-off-by: NMark Brown <broonie@kernel.org>
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- 16 6月, 2015 1 次提交
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由 Cyrille Pitchen 提交于
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs. When FIFOs are enabled, they can either work in SINGLE data mode or MULTIPLE data mode. The selected mode depends on the configuration of the SPI controller (see below). In SINGLE data mode (or legacy mode), for a single I/O access, only one data can be read from the Receive Data Register (RDR) or written into the Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up to 4 data can be read from the RDR or up 2 data can be written into the TDR in a single 32bit I/O access. So programmers should take good care of the width of the I/O access to read/write the right number of data. The exact number of read/written data depends on both the I/O access width and the data width (from 8 up to 16 bits). To enable the FIFO feature a "atmel,fifo-size" property must be set to provide the maximum number of data (not bytes) the RX and TX FIFOs can store. Hence a 32 data FIFO can always store up to 32 data unrelated with the actual data width. When FIFOs are enabled, the RX one is forced to operate in SINGLE data mode because this driver configures the spi controller as a master. In master mode only, the Received Data Register has an additionnal Peripheral Chip Select field, which prevents us from reading more than a single data at each register access. Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a 8bit data size is used, only two data by access could be written into the Transmit Data Register. Indeed the first data has to be written into the lowest 16 bits whereas the second data has to be written into the highest 16 bits of the TDR. When DMA transfers are used to send data, we don't rework the transmit buffer to cope with this hardware limitation: the additional copies required to prepare a new input buffer suited to both the DMA controller and the spi controller would waste all the benefit of the DMA transfer. Instead, the DMA controller is configured to write only one data at time into the TDR. In pio mode, two data are written in the TDR in a single access. Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 15 6月, 2015 1 次提交
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由 Mathias Krause 提交于
Constify the ACPI device ID array, it doesn't need to be writable at runtime. Signed-off-by: NMathias Krause <minipli@googlemail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 13 6月, 2015 2 次提交
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由 Ranjit Waghmode 提交于
This patch adds support for GQSPI controller driver used by Zynq Ultrascale+ MPSoC Signed-off-by: NRanjit Waghmode <ranjit.waghmode@xilinx.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Mirza Krak 提交于
Add support for "sleep" state of pinctrl. Signed-off-by: NMirza Krak <mirza.krak@hostmobility.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 11 6月, 2015 1 次提交
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由 Murali Karicheri 提交于
SPI hardware spec for Keystone specify a lower value of 0 for pre-scale divider which determine what max value of spi clock (spi-max-frequency) the device can support. This translates to a clock divider of 2. So fix the lower limit value used for the boundary check in davinci_spi_get_prescale() function to 1 so that a maximum of spi device clock rate / 2 is possible to be set for spi-max-frequency. Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com> Acked-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 10 6月, 2015 3 次提交
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由 Haikun Wang 提交于
In current driver, we increase actual_length in the following way: message->actual_length += dspi_xxx_transfer() It has two defects. First, transmitting maybe in process when the function call finished and we don't know the transmitting result in this moment. Secondly, the last sentence in function before returning is accessing the SPI register and trigger the data transmitting. If we enable interrupt, interrupt may be generated before function return and we also have the same sentence "message->actual_length += dspi_xxx_transfer()" in the IRQ handler. And usually dspi_xxx_transfer will trigger a new IRQ. The original dspi_xxx_transfer call may return when no new IRQ generate. This may mess the variable spi_message->actual_length. Now we increase the variable in the IRQ handler and only when we get the TCF or EOQ interrupt And we get the transmitted data length from the SPI transfer counter instead of the function return value. Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Haikun Wang 提交于
DSPI module has two optional interrupts when complete data transfer. One is EOQ interrupt, the other one is TCF interrupt. EOQ indicates a queue of data frame has been transmitted. TCF indicates a frame has been transmitted. This patch enable support TCF mode. Driver binds a correct interrupt mode to every compatible string. User should use the correct compatible string in the dts node. Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Cyrille Pitchen 提交于
This patch relies on the CSAAT (Chip Select Active After Transfer) feature introduced by the version 2 of the spi controller. This new mode allows to use properly the internal chip-select output pin of the spi controller instead of using external gpios. Consequently, the "cs-gpios" device-tree property becomes optional. When the new CSAAT bit is set into the Chip Select Register, the internal chip-select output pin remains asserted till both the following conditions become true: - the LASTXFER bit is set into the Control Register (or the Transmit Data Register) - the Transmit Data Register and its shift register are empty. WARNING: if the LASTXFER bit is set into the Control Register then new data are written into the Transmit Data Register fast enough to keep its shifter not empty, the chip-select output pin remains asserted. Only when the shifter becomes empty, the chip-select output pin is unasserted. When the CSAAT bit is clear in the Chip Select Register, the LASTXFER bit is ignored in both the Control Register and the Transmit Data Register. The internal chip-select output pin remains active as long as the Transmit Data Register or its shift register are not empty. Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 09 6月, 2015 1 次提交
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由 Daniel Mack 提交于
Generic DMA support was already implemented by commit cd7bed00 ("spi/pxa2xx: break out the private DMA API usage into a separate file") which moved all the legacy PXA DMA implementation code into its own file. With generic DMA available for PXA, we can now just trash this file. Signed-off-by: NDaniel Mack <zonque@gmail.com> Acked-by: NMark Brown <broonie@linaro.org> [respin after pxa dmaengine support upstream] Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 05 6月, 2015 3 次提交
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由 Jarkko Nikula 提交于
General register located in LPSS SPI private register space is not found in upcoming Intel LPSS platforms. Access it conditionally depending is it defined in configuration. Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Jarkko Nikula 提交于
Some of the Intel LPSS SPI properties will be different in upcoming platforms compared to existing Lynxpoint and BayTrail/Braswell. LPSS SPI private registers will be at different offset and there will be changes in individual registers and default FIFO thresholds too. Add configuration for these differences and use them in runtime based on LPSS SSP type. With this change private registers offset autodetection becomes needless. Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Jarkko Nikula 提交于
Intel LPSS SPI properties differ between between platforms. Now private registers offset 0x400 or 0x800 is autodetected but there is need to support also other offset and handle a few other differences. Prepare for that by splitting the LPSS_SSP type into compatible hardware types and set it now based on PCI or ACPI ID. That type will be used to set properties that differ between current and upcoming platforms. Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 03 6月, 2015 1 次提交
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由 Martin Sperl 提交于
The case where spi_master sets the flags SPI_MASTER_MUST_RX/TX while CONFIG_HAS_DMA is unset (which is unlikley) together with a driver that reuses spi_messages with rx/tx_buff set to NULL, can result in: * data disclosure over the SPI (for tx_buf == NULL) * memory corruption (for rx_buf == NULL) This happenes when dummy_rx/dummy_tx are changing address due to krealloc or free and an allocation of the memory by a different part of the kernel. Signed-off-by: NMartin Sperl <kernel@martin.sperl.org> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 02 6月, 2015 2 次提交
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由 Hiep Cao Minh 提交于
To reduce complexity of code, drop "ret" then qspi_transfer_out_in function should return the value of "qspi_trigger_transfer_out_in" directly. Signed-off-by: NHiep Cao Minh <cm-hiep@jinso.co.jp> Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Hiep Cao Minh 提交于
The name of "qspi_trigger_transfer_out_int" function should be "qspi_trigger_transfer_out_in" without "t". Signed-off-by: NHiep Cao Minh <cm-hiep@jinso.co.jp> Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 28 5月, 2015 1 次提交
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由 Gregory CLEMENT 提交于
The commit df59fa7f "spi: orion: support armada extended baud rates" made the assumptions that all the Armada SoCs supported the same maximum frequency. However, according the hardware datasheet, the maximum frequency supported by the Armada 370 SoC is tclk/4, for the Armada XP, Armada 38x and Armada 39x SoCs the limitation is 50MHz and for the Armada 375 it is tclk/15. This patch introduces new compatible strings to handle all these case. In order to be future proof a compatible was created for each SoC even if currently some SoCs seem using the same IP. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 26 5月, 2015 3 次提交
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由 Qipan Li 提交于
USP-based SPI need a disable and enable, otherwise it doesn't work. this patch adds it as HW initialization. Signed-off-by: NQipan Li <Qipan.Li@csr.com> Signed-off-by: NBarry Song <Baohua.Song@csr.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Qipan Li 提交于
this job has been done by spi core. Signed-off-by: NQipan Li <Qipan.Li@csr.com> Signed-off-by: NBarry Song <Baohua.Song@csr.com> Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Gregory CLEMENT 提交于
The commit df59fa7f "spi: orion: support armada extended baud rates" was too optimistic for the maximum baud rate that the Armada SoCs can support. According to the hardware datasheet the maximum frequency supported by the Armada 370 SoC is tclk/4. But for the Armada XP, Armada 38x and Armada 39x SoCs the limitation is 50MHz and for the Armada 375 it is tclk/15. Currently the armada-370-spi compatible is only used by the Armada 370 and the Armada XP device tree. On Armada 370, tclk cannot be higher than 200MHz. In order to be able to handle both SoCs, we can take the minimum of 50MHz and tclk/4. A proper solution is adding a compatible string for each SoC, but it can't be done as a fix for compatibility reason (we can't modify device tree that have been already released) and it will be part of a separate patch. Fixes: df59fa7f (spi: orion: support armada extended baud rates) Reported-by: NKostya Porotchkin <kostap@marvell.com> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NMark Brown <broonie@kernel.org> Cc: <stable@vger.kernel.org>
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- 25 5月, 2015 4 次提交
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由 Michael Welling 提交于
If a valid GPIO is specified but cannot be requested by the driver, print a message and error out of omap2_mcspi_setup. Signed-off-by: NMichael Welling <mwelling@ieee.org> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Michael Welling 提交于
The OMAP2_MCSPI_CHCONF_FORCE must be toggled even when using GPIO chip selects. This patch conditionally calls the omap2_mcspi_set_cs function to do so when using GPIO chip selects. Signed-off-by: NMichael Welling <mwelling@ieee.org> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Michael Welling 提交于
The core spi driver swaps the polarity of the enable based on SPI_CS_HIGH. The omap2 controller has an internal configuration register bit called OMAP2_MCSPI_CHCONF_EPOL to handle active high chip selects as well. So we have to revert swap the polarity back for the correct setting of the OMAP2_MCSPI_CHCONF_FORCE bit in omap2_mcspi_set_cs. Signed-off-by: NMichael Welling <mwelling@ieee.org> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Michael Welling 提交于
The core spi driver handles the delay between transactions. This is a remanant from the transfer_one conversion. Signed-off-by: NMichael Welling <mwelling@ieee.org> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 22 5月, 2015 2 次提交
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由 Jane Wan 提交于
Incorrect condition is used in spin_event_timeout(). When the TX is done, the SPIE_NF bit in ESPI_SPIE register is set to 1 to indicate the Tx FIFO is not full. If the bit is 0, it indicates the Tx FIFO is full. Due to this error, if the Tx FIFO is full at the beginning, but becomes not full after handling the Rx FIFO (the SPIE_NF bit is set), the spin_event_timeout() returns with timeout occurred. It causes the interrupt handler not to send completion notification to the thread that called wait_for_complete() waiting for the notification. Signed-off-by: NJane Wan <Jane.Wan@gainspeed.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Haikun Wang 提交于
SPI chip select signal need to keep asserted between several spi_transfer in the same spi_message usually. But the driver will de-assert CS signal and the assert it between serval spi_transfer in the same spi_message under some condiations. This patch fix the bug. Here is an example: Assume you have two variables like the following, struct spi_transfer a; struct spi_transfer b; if you send a spi_message only includes 'a' first, and then you send a spi_message includes 'a' and 'b' but without resetting 'a'. Driver will de-assert CS and then assert CS between 'a' and 'b'. Signed-off-by: NHaikun Wang <haikun.wang@freescale.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 21 5月, 2015 1 次提交
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由 Qipan Li 提交于
USP is a general purpose serial port in SiRFSoC, which can work as SPI. the most data flow of USP and pure SPI is same with main differences in registers layout. this patch moves registers layout to private data, and use flags to differentiate other minor differences between prima2-spi, prima2-usp and atlas7-usp for hardware configuration. Signed-off-by: NQipan Li <Qipan.Li@csr.com> Signed-off-by: NBarry Song <Baohua.Song@csr.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 13 5月, 2015 1 次提交
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由 Michael Welling 提交于
GPIO chip select patch series appears to have broken the native chip select support. This patch pulls the manual native chip select toggling out of the transfer_one routine and adds a set_cs routine. Tested natively on AM3354 with SPI serial flash on spi0cs0. Reported-by: NNishanth Menon <nm@ti.com> Signed-off-by: NMichael Welling <mwelling@ieee.org> Tested-by: NNishanth Menon <nm@ti.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 12 5月, 2015 4 次提交
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由 kbuild test robot 提交于
Signed-off-by: NFengguang Wu <fengguang.wu@intel.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Martin Sperl 提交于
fixes several warnings/error emmitted by the kbuild system: * warn: cast from pointer to integer of different size using size_t instead of u32 * error: 'SZ_4K' undeclared moved to PAGE_SIZE and PAGE_MASK instead Review showed also a typo in the same code where tx_buff was checked twice instead of checking both rx and tx_buff. Reported by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: NMartin Sperl <kernel@martin.sperl.org> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Martin Sperl 提交于
Conditions per spi_transfer are: * transfer.len >= 96 bytes (to avoid mapping overhead costs) * transfer.len < 65536 bytes (limitaion by spi-hw block - could get extended) * an individual scatter/gather transfer length must be a multiple of 4 for anything but the last transfer - spi-hw block limit. (some shortcut has been taken in can_dma to avoid unnecessary mapping of pages which, for which there is a chance that there is a split with a transfer length not a multiple of 4) If it becomes a necessity these restrictions can get removed by additional code. Note that this patch requires a patch to dma-bcm2835.c by Noralf to enable scatter-gather mode inside the dmaengine, which has not been merged yet. That is why no patch to arch/arm/boot/dts/bcm2835.dtsi is included - the code works as before without dma when tx/rx are not set, but it writes a message warning about dma not used: spi-bcm2835 20204000.spi: no tx-dma configuration found - not using dma mode To enable dma-mode add the following lines to the device-tree: dmas = <&dma 6>, <&dma 7>; dma-names = "tx", "rx"; Tested-by: Noralf Trønnes <noralf@tronnes.org> (private communication) Signed-off-by: NMartin Sperl <kernel@martin.sperl.org> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Martin Sperl 提交于
Fix a race (with some kernel configurations) where a queued master->pump_messages runs and frees dummy_tx/rx before spi_unmap_msg is running (or is finished). This results in the following messages: BUG: Bad page state in process page:db7ba030 count:0 mapcount:0 mapping: (null) index:0x0 flags: 0x200(arch_1) page dumped because: PAGE_FLAGS_CHECK_AT_PREP flag set ... Reported-by: NNoralf Trønnes <noralf@tronnes.org> Suggested-by: NNoralf Trønnes <noralf@tronnes.org> Tested-by: NNoralf Trønnes <noralf@tronnes.org> Signed-off-by: NMartin Sperl <kernel@martin.sperl.org> Signed-off-by: NMark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
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- 11 5月, 2015 1 次提交
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由 Fabio Estevam 提交于
Remove unneeded variable used to store return value. The semantic patch that makes this change is available in scripts/coccinelle/misc/returnvar.cocci. More information about semantic patching is available at http://coccinelle.lip6.fr/Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 09 5月, 2015 1 次提交
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由 Michael Welling 提交于
If GPIO chip select is specified, request the GPIO in the setup function and release it in the cleanup function. Signed-off-by: NMichael Welling <mwelling@ieee.org> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 08 5月, 2015 1 次提交
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由 Michael Welling 提交于
Switches from transfer_one_message to transfer_one to prepare driver for use of GPIO chip selects. Signed-off-by: NMichael Welling <mwelling@ieee.org> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 07 5月, 2015 3 次提交
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由 Hiep Cao Minh 提交于
To reduce indentation and complexity of code, insteeds of returning zero the function rspi_dma_check_then_transfer should return rspi_dma_transfer directly after checking error. Signed-off-by: NHiep Cao Minh <cm-hiep@jinso.co.jp> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Qipan Li 提交于
Signed-off-by: NQipan Li <Qipan.Li@csr.com> Signed-off-by: NBarry Song <Baohua.Song@csr.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Qipan Li 提交于
move spi controller's gpio request work out from probe() to spi device register stage, so after spi device register spi controller can deactive device's gpio chipselect. old code can't do it because gpio request has not be done until device register is finised in spi_bitbang_start. and add cleanup function to free CS gpio. Signed-off-by: NQipan Li <Qipan.Li@csr.com> Signed-off-by: NBarry Song <Baohua.Song@csr.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 06 5月, 2015 1 次提交
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由 Geert Uytterhoeven 提交于
The GPIO subsystem provides dummy GPIO consumer functions if GPIOLIB is not enabled. Hence drivers that depend on GPIOLIB, but use GPIO consumer functionality only, can still be compiled if GPIOLIB is not enabled. Relax the dependency on GPIOLIB if COMPILE_TEST is enabled, where appropriate. Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 04 5月, 2015 1 次提交
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由 Yoshinori Sato 提交于
I got following error on CONFIG_GPIOLIB=n. drivers/spi/spi-bcm2835.c: In function 'chip_match_name': drivers/spi/spi-bcm2835.c:356:21: error: dereferencing pointer to incomplete type 'struct gpio_chip' return !strcmp(chip->label, data); ^ drivers/spi/spi-bcm2835.c: In function 'bcm2835_spi_setup': drivers/spi/spi-bcm2835.c:382:9: error: implicit declaration of function 'gpiochip_find' [-Werror=implicit-function-declaration] chip = gpiochip_find("pinctrl-bcm2835", chip_match_name); ^ drivers/spi/spi-bcm2835.c:382:7: warning: assignment makes pointer from integer without a cast [-Wint-conversion] chip = gpiochip_find("pinctrl-bcm2835", chip_match_name); ^ drivers/spi/spi-bcm2835.c: In function 'chip_match_name': drivers/spi/spi-bcm2835.c:357:1: warning: control reaches end of non-void function [-Wreturn-type] } ^ Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: NMark Brown <broonie@kernel.org>
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