1. 31 3月, 2015 1 次提交
  2. 05 3月, 2015 2 次提交
  3. 25 2月, 2015 3 次提交
  4. 29 1月, 2015 5 次提交
  5. 26 1月, 2015 1 次提交
  6. 14 1月, 2015 1 次提交
  7. 09 1月, 2015 1 次提交
  8. 07 1月, 2015 1 次提交
  9. 05 1月, 2015 3 次提交
  10. 17 12月, 2014 1 次提交
  11. 05 12月, 2014 2 次提交
    • D
      clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers · 65b5732d
      Doug Anderson 提交于
      Some 32-bit (ARMv7) systems are architected like this:
      
      * The firmware doesn't know and doesn't care about hypervisor mode and
        we don't want to add the complexity of hypervisor there.
      
      * The firmware isn't involved in SMP bringup or resume.
      
      * The ARCH timer come up with an uninitialized offset (CNTVOFF)
        between the virtual and physical counters.  Each core gets a
        different random offset.
      
      * The device boots in "Secure SVC" mode.
      
      * Nothing has touched the reset value of CNTHCTL.PL1PCEN or
        CNTHCTL.PL1PCTEN (both default to 1 at reset)
      
      On systems like the above, it doesn't make sense to use the virtual
      counter.  There's nobody managing the offset and each time a core goes
      down and comes back up it will get reinitialized to some other random
      value.
      
      This adds an optional property which can inform the kernel of this
      situation, and firmware is free to remove the property if it is going
      to initialize the CNTVOFF registers when each CPU comes out of reset.
      
      Currently, the best course of action in this case is to use the
      physical timer, which is why it is important that CNTHCTL hasn't been
      changed from its reset value and it's a reasonable assumption given
      that the firmware has never entered HYP mode.
      
      Note that it's been said that on ARMv8 systems the firmware and
      kernel really can't be architected as described above.  That means
      using the physical timer like this really only makes sense for ARMv7
      systems.
      Signed-off-by: NDoug Anderson <dianders@chromium.org>
      Signed-off-by: NSonny Rao <sonnyrao@chromium.org>
      Reviewed-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      65b5732d
    • S
      clocksource: arch_timer: Fix code to use physical timers when requested · 0b46b8a7
      Sonny Rao 提交于
      This is a bug fix for using physical arch timers when
      the arch_timer_use_virtual boolean is false.  It restores the
      arch_counter_get_cntpct() function after removal in
      
      0d651e4e "clocksource: arch_timer: use virtual counters"
      
      We need this on certain ARMv7 systems which are architected like this:
      
      * The firmware doesn't know and doesn't care about hypervisor mode and
        we don't want to add the complexity of hypervisor there.
      
      * The firmware isn't involved in SMP bringup or resume.
      
      * The ARCH timer come up with an uninitialized offset between the
        virtual and physical counters.  Each core gets a different random
        offset.
      
      * The device boots in "Secure SVC" mode.
      
      * Nothing has touched the reset value of CNTHCTL.PL1PCEN or
        CNTHCTL.PL1PCTEN (both default to 1 at reset)
      
      One example of such as system is RK3288 where it is much simpler to
      use the physical counter since there's nobody managing the offset and
      each time a core goes down and comes back up it will get reinitialized
      to some other random value.
      
      Fixes: 0d651e4e ("clocksource: arch_timer: use virtual counters")
      Cc: stable@vger.kernel.org
      Signed-off-by: NSonny Rao <sonnyrao@chromium.org>
      Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
      Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      0b46b8a7
  12. 03 12月, 2014 1 次提交
  13. 01 12月, 2014 1 次提交
  14. 26 11月, 2014 2 次提交
  15. 24 11月, 2014 10 次提交
  16. 19 11月, 2014 2 次提交
  17. 18 11月, 2014 1 次提交
  18. 28 10月, 2014 1 次提交
  19. 27 10月, 2014 1 次提交