1. 05 9月, 2019 11 次提交
  2. 12 8月, 2019 6 次提交
  3. 29 7月, 2019 2 次提交
  4. 01 7月, 2019 3 次提交
  5. 27 6月, 2019 1 次提交
  6. 08 7月, 2019 1 次提交
  7. 20 6月, 2019 1 次提交
  8. 16 6月, 2019 1 次提交
  9. 04 6月, 2019 1 次提交
  10. 03 6月, 2019 1 次提交
  11. 31 5月, 2019 1 次提交
    • O
      habanalabs: add WARN in case of bad MMU mapping · 747bf88c
      Oded Gabbay 提交于
      This patch checks if an MMU mapping is erroneous in that the physical
      address that is being mapped is NOT divisible by the page size.
      
      If that thing happens, then the H/W will issue a transaction which will be
      translated to a wrong address, because part of the address will not be
      taken (the remainder of address/page size).
      
      Because the physical address is being handled by the driver, a WARN is
      suitable here as it implies a bug in the driver code itself and not a user
      bug.
      Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
      747bf88c
  12. 29 5月, 2019 6 次提交
    • O
      habanalabs: remove DMA mask hack for Goya · 2a51558c
      Oded Gabbay 提交于
      This patch removes the non-standard DMA mask setting for Goya. Now that
      the device CPU goes through the MMU, we are not limited to allocating the
      CPU accessible memory area in the address space of under 39 bits.
      Therefore, we don't need to set the DMA masking twice during
      initialization, a practice that is not working on POWER architecture.
      
      The patch sets the DMA mask to 48 bits once during the initialization. The
      address of the CPU accessible memory area is configured to the MMU and the
      matching VA is given to the device CPU.
      Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
      2a51558c
    • O
      habanalabs: set Goya CPU to use ASIC MMU · f09415f5
      Oded Gabbay 提交于
      This patch configures the Goya CPU to actually go through the MMU for
      translation. The configuration is done after the configuration of the
      relevant MMU mappings.
      Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
      f09415f5
    • O
      habanalabs: add MMU mappings for Goya CPU · 95b5a8b8
      Oded Gabbay 提交于
      This patch adds the necessary MMU mappings for the Goya CPU to access the
      device DRAM and the host memory.
      
      The first 256MB of the device DRAM is being mapped. That's where the F/W
      is running.
      
      The 2MB area located on the host memory for the purpose of communication
      between the driver and the device CPU is also being mapped.
      Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
      95b5a8b8
    • O
      habanalabs: initialize MMU context for driver · 7aa2227a
      Oded Gabbay 提交于
      This patch initializes the MMU structures for the kernel context. This is
      needed before we can configure mappings for the kernel context.
      Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
      7aa2227a
    • O
      habanalabs: de-couple MMU and VM module initialization · 37d68ce5
      Oded Gabbay 提交于
      This patch initializes the MMU S/W structures before the VM S/W
      structures, instead of doing that as part of the VM S/W initialization.
      
      This is done because we need to configure some MMU mappings for the kernel
      context, before the VM is initialized. The VM initialization can't be
      moved earlier because it depends on the size of the DRAM, which is
      retrieved from the device CPU. Communication with the device CPU will
      require the MMU mappings to be configured and hence the de-coupling.
      Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
      37d68ce5
    • O
      habanalabs: initialize device CPU queues after MMU init · 0b28d26b
      Oded Gabbay 提交于
      This patch changes the order of H/W IP initializations. The MMU needs to
      be initialized before the device CPU queues, because the CPU will go
      through the ASIC MMU in order to reach the host memory (where the queues
      are located).
      Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
      0b28d26b
  13. 06 6月, 2019 1 次提交
  14. 04 6月, 2019 1 次提交
  15. 30 5月, 2019 3 次提交