These patches rework the pci code for the sh architecture.

Currently each board implements some kind of ioport to address mapping.
Some boards use generic_io_base others try passing addresses as io ports.
This is the first set of patches that try to unify the pci code as much
as possible to avoid duplicated code. This will in the end lead to fewer
lines board specific code and more generic code.

This patch makes sure a struct pci_channel pointer is passed along to
various pci functions such as pci_read_reg(), pci_write_reg(),
pci_fixup_pcic(), sh7751_pcic_init() and sh7780_pcic_init().
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

PCI still doesn't work on sh7785lcr 29bit 256M map mode.

On SH7785, PCI -> SHwy address translation is not base+offset but
somewhat like base|offset (See HW Manual (rej09b0261) Fig. 13.11).
So, you can't export CS2,3,4,5 by 256M at CS2 (results CS0,1,2,3
exported, I guess).  There are two candidates.

a) 128M@CS2 + 128M@CS4
b) 512M@CS0

Attached patch is B. It maps 512M Byte at 0 independently of memory
size. It results CS0 to CS6 and perhaps some more being accessible
from PCI.

Tested on
7785lcr 29bit 128M map
7785lcr 29bit 256M map
(NOT tested on 32bit)
Signed-off-by: NTakashi YOSHII <yoshii.takashi@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Fix the problem that cannot work a PCI device when 32-bit physical
address mode.
Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Fix the problem that cannot work a PCI device when system memory size is
256Mbyte in 29bit address mode.
Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch makes sure ctrl_inN/outN are used instead of inN/outN for on chip
pci registers. Without this patch addresses may be adjusted using the value
in generic_io_base. This patch makes it possible to set generic_io_base and
have pci without reading and writing all over the place.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Acked-by: NKatsuya MATSUBARA <matsu@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch removes the sh778x specific pci code that pokes in the
interrupt controller and overwrites things. The new and improved IRL
code manages this in plat_irq_setup() and plat_irq_setup_pins()
instead.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds support for the SH7780-based Solution Engine reference board.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.zh@hitachi.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds preliminary support for the SH7785-based Highlander board.
Some of the Highlander support code is reordered so that most of it
can be reused directly.

This also plugs in missing SH7785 checks in the places that need it,
as this is the first board to support the CPU.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This drops the various IRQ headers that were floating around
and primarily providing hardcoded IRQ definitions for the
various CPU subtypes. This quickly got to be an unmaintainable
mess, made even more evident by the subtle breakage introduced
by the SH-2 and SH-2A changes.

Now that subtypes are able to register IRQ maps directly, just
rip all of the headers out.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

A few of these managed to sneak back in, get rid of them once
and for all.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This cleans up quite a lot of the PCI mess that we
currently have, and attempts to consolidate the
duplication in the SH7780 and SH7751 PCI controllers.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds support for the Renesas SH7780 development boards,
R7780RP and R7780MP.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>