In case of the last page containing bitflips (ret > 0),
spinand_mtd_read() will return that number of bitflips for the last
page while it should instead return max_bitflips like it does when the
last page read returns with 0.
Signed-off-by: NWeixiong Liao <liaoweixiong@allwinnertech.com>
Reviewed-by: NBoris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
Cc: stable@vger.kernel.org
Fixes: 7529df46 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Add initial support for Paragon Technology
PN26G01Axxxxx and PN26G02Axxxxx SPI NAND

Datasheets available at
http://www.xtxtech.com/upfile/2016082517274590.pdf
http://www.xtxtech.com/upfile/2016082517282329.pdfSigned-off-by: NJeff Kletsky <git-commits@allycomm.com>
Reviewed-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

It is wanted to use MTK NAND driver with GPL-2.0 or MIT license.
But now it is only licensed as GPL-2.0, so re-license it as dual
MIT/GPL.
Signed-off-by: NXiaolei Li <xiaolei.li@mediatek.com>
Acked-by: NJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Acked-by: NRyder Lee <ryder.lee@mediatek.com>
Acked-by: NRafał Miłecki <rafal@milecki.pl>
Acked-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Acked-by: NBoris Brezillon <boris.brezillon@collabora.com>
Acked-by: NWen Yang <yellowriver2010@hotmail.com>
Acked-by: NDan Carpenter <dan.carpenter@oracle.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NRogerCC Lin <rogercc.lin@mediatek.com>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The variable block_size is being assigned to itself and to
geo->ecc_chunk_size.  Clean up the double assignment by removing
the assignment to itself.

Addresses-Coverity: ("Evaluation order violation")
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Added brcm,brcmnand-v7.3 as possible compatible string to support
brcmnand controller v7.3.
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

This change adds support for brcm NAND v7.3 controller. This controller
uses a newer version of flash_dma engine and change mostly implements
these differences.
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Refactored NAND ECC and CMD address configuration code to use helper
functions.
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

If mtd_oops is in progress, switch to polling during NAND command
completion instead of relying on DMA/interrupts so that the mtd_oops
buffer can be completely written in the assigned NAND partition.
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Added a flag to indicate a panic_write so that low level drivers can
use it to take required action where applicable, to ensure oops data
gets written to assigned mtd device.
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Add support for Macronix NAND read retry.

Macronix NANDs support specific read operation for data recovery,
which can be enabled with a SET_FEATURE.
Driver checks byte 167 of Vendor Blocks in ONFI parameter page table
to see if this high-reliability function is supported.
Signed-off-by: NMason Yang <masonccyang@mxic.com.tw>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

NOTICE THAT:

"...we don't know whether we need fallthroughs or breaks here and this
is just a change to avoid having new warnings when switching to
-Wimplicit-fallthrough but this change might be entirely wrong."[1]

See the original thread of discussion here:

https://lore.kernel.org/patchwork/patch/1036251/

So, in preparation to enabling -Wimplicit-fallthrough, this patch silences
the following warnings:

drivers/mtd/nand/onenand/onenand_base.c: In function ‘onenand_check_features’:
drivers/mtd/nand/onenand/onenand_base.c:3264:6: warning: this statement may fall through [-Wimplicit-fallthrough=]
   if (ONENAND_IS_DDP(this))
      ^
drivers/mtd/nand/onenand/onenand_base.c:3284:2: note: here
  case ONENAND_DEVICE_DENSITY_2Gb:
  ^~~~
drivers/mtd/nand/onenand/onenand_base.c:3288:17: warning: this statement may fall through [-Wimplicit-fallthrough=]
   this->options |= ONENAND_HAS_UNLOCK_ALL;
drivers/mtd/nand/onenand/onenand_base.c:3290:2: note: here
  case ONENAND_DEVICE_DENSITY_1Gb:
  ^~~~

Warning level 3 was used: -Wimplicit-fallthrough=3

Also, notice that this patch doesn't change any functionality. See the
most recent thread of discussion here:

https://lore.kernel.org/patchwork/patch/1077395/

This patch is part of the ongoing efforts to enable
-Wimplicit-fallthrough.

[1] https://lore.kernel.org/lkml/20190509085318.34a9d4be@xps13/

Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Suggested-by: NBoris Brezillon <boris.brezillon@collabora.com>
Suggested-by: NKees Cook <keescook@chromium.org>
Signed-off-by: NGustavo A. R. Silva <gustavo@embeddedor.com>
Reviewed-by: NKees Cook <keescook@chromium.org>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The GigaDevice GD5F1GQ4UFxxG SPI NAND is in current production devices
and, while it has the same logical layout as the E-series devices,
it differs in the SPI interfacing in significant ways.

This support is contingent on previous commits to:

  * Add support for two-byte device IDs
  * Define macros for page-read ops with three-byte addresses

http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/Signed-off-by: NJeff Kletsky <git-commits@allycomm.com>
Reviewed-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The GigaDevice GD5F1GQ4UFxxG SPI NAND utilizes two-byte device IDs.

http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/Signed-off-by: NJeff Kletsky <git-commits@allycomm.com>
Reviewed-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The GigaDevice GD5F1GQ4UFxxG SPI NAND utilizes three-byte addresses
for its page-read ops.

http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/Signed-off-by: NJeff Kletsky <git-commits@allycomm.com>
Reviewed-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

This change supports nand-ecc-step-size and nand-ecc-strength fields in
brcmnand DT node to be optional.
see: Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt

If both nand-ecc-strength and nand-ecc-step-size are not specified in
device tree node for NAND, raw NAND layer does detect ECC information by
reading ONFI extended parameter page for parts using ONFI >= 2.1.
In case of non-ONFI NAND parts there could be a nand_id table entry with
ECC information. If there is valid device tree entry for nand-ecc-strength
and nand-ecc-step-size fields it still shall override the detected values.
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

nand-ecc-strength and nand-ecc-step-size can be made optional as
brcmnand driver can support using raw NAND layer detected values.
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The gpmi driver performance suffers from NAND operations being split
in multiple small DMA transfers. This has been forced by the NAND layer
in the former days, but now with exec_op we can use the controller as
intended.

With this patch gpmi_nfc_exec_op becomes the main entry point to NAND
operations. Here all instructions are collected and chained as separate
DMA transfers. In the end whole chain is fired and waited to be
finished. gpmi_nfc_exec_op only does the hardware operations, bad block
marker swapping and buffer scrambling is done by the callers. It's worth
noting that the nand_*_op functions always take the buffer lengths for
the data that the NAND chip actually transfers. When doing BCH we have
to calculate the net data size from the raw data size in some places.

This patch has been tested with 2048/64 and 2048/128 byte NAND on
i.MX6q. mtd_oobtest, mtd_subpagetest and mtd_speedtest run without
errors. nandbiterrs, nandpagetest and nandsubpagetest userspace tests
from mtdutils run without errors and UBIFS can successfully be mounted.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The mxs dma driver uses the flags parameter in dmaengine_prep_slave_sg() for
custom flags, but still uses the dmaengine specific names of the flags.
Do a little bit better and at least give the flag a custom name.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The mxs dma driver can do PIO transfers. A pointer to the PIO words
to transfer is passed in the struct scatterlist * argument of
dmaengine_prep_slave_sg(). It's quite ugly and non obvious to cast
u32 * to struct scatterlist * each time when calling
dmaengine_prep_slave_sg(), so add a static inline wrapper function
to be called by the user along with a description what is going on.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The DMA_PREP_INTERRUPT flag is no longer needed by the mxs DMA driver,
drop it.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The mxs dma driver insists on having the DMA_PREP_INTERRUPT flag set
on all but the first transfer. There's no need to let the user set this
flag, the driver can do it internally whenever it needs it. Drop
handling of this flag from the driver.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The gpmi driver aggressively en/disables the clocks between operations
which has significant performance cost. Use runtime PM to get rid of
this bottleneck.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The i.MX23 specific option read code is called right after nand_scan. We
can rely on the NAND core having disabled the chipselect, so there's no
point in restoring the original chip select after NAND operations. Drop
it.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

gpmi_ecc_read_page_data uses the page parameter only for a debug printf,
so we can drop the parameter and the debug printf. Moving the oob
delivery from gpmi_ecc_read_page_data to gpmi_ecc_read_page makes the
oob_required parameter unnecessary aswell.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The driver calls nand_read_page_op without a buffer passed and then
calls chip->legacy.read_buf to read the buffer afterwards which is
the same as passing the buffer nand_read_page_op in the first place.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

this->page_buffer_virt and this->payload_virt are always set to the same
value, so drop the former and just use the latter. Same for
this->page_buffer_virt and this->payload_virt.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The "private" member of struct gpmi_nand_data isn't used anywhere.
Remove it.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

This moves the whole driver into a single C file. The filename gpmi-lib
implies that it implements library functions, but in fact there are
several cases where functions in gpmi-lib.c call back into functions in
gpmi-nand.c. With this one has to constantly jump between those two
files, so moving it into a single file improves readability, even when
the file gets quite large.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Replace the different operation tracing functions with a call to
nand_op_trace.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The NAND core has a NAND operation tracing function, but it can only
be used by drivers using the generic option parser from the NAND core.
Export the tracing function as a static inline function in rawnand.h
so that drivers implementing exec_op directly do not have to write their
own operation tracing.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

One main goal of the function mtk_nfc_update_ecc_stats is to check
whether sectors are all empty. If they are empty, set these sectors's
data buffer and OOB buffer as 0xff.

But now, the sector OOB buffer pointer is wrongly assigned. We always
do memset from sector 0.

To fix this issue, pass start sector number to make OOB buffer pointer
be properly assigned.

Fixes: 1d6b1e46 ("mtd: mediatek: driver for MTK Smart Device")
Signed-off-by: NXiaolei Li <xiaolei.li@mediatek.com>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Currently, we only check how many CE# pins are set in device tree.
But it should be necessary to check whether CE# pin setting is
duplicated or if CE# pin index exceeds the maximum CE# number that
controller supports.

So, add validity check to avoid these invalid settings.
Signed-off-by: NXiaolei Li <xiaolei.li@mediatek.com>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Currently, we expand RE# low level time by choosing the max value
between RE# pulse width and RE# access time, and sample data at the
rising edge of RE#.

Then, if RE# access time is bigger than RE# pulse width, the real
read cycle time may be more than NAND SPEC required. This makes
read performance be worse than that expected.

This patch improves data sampling timing by calculating RE# low level
time according to RE# pulse width. If RE# access time is bigger than
RE# pulse width, then delay sampling data timing.

The result of contrast test base on MT2712 evaluat board is as follow.

nand: Micron MT29F16G08ADBCAH4
nand: 2048 MiB, SLC, erase size: 256 KiB, page size: 4096, OOB size: 224
NFI 2x clock rate: 124800000 HZ.

Read speed without this patch:
mtd_speedtest: page read speed is 14012 KiB/s
mtd_speedtest: 2 page read speed is 14860 KiB/s

Read speed with this patch:
mtd_speedtest: page read speed is 18724 KiB/s
mtd_speedtest: 2 page read speed is 18713 KiB/s
Signed-off-by: NXiaolei Li <xiaolei.li@mediatek.com>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

At present, the flow of calculating AC timing of read/write cycle in SDR
mode is that:
At first, calculate high hold time which is valid for both read and write
cycle using the max value between tREH_min and tWH_min.
Secondly, calculate WE# pulse width using tWP_min.
Thridly, calculate RE# pulse width using the bigger one between tREA_max
and tRP_min.

But NAND SPEC shows that Controller should also meet write/read cycle time.
That is write cycle time should be more than tWC_min and read cycle should
be more than tRC_min. Obviously, we do not achieve that now.

This patch corrects the low level time calculation to meet minimum
read/write cycle time required. After getting the high hold time, WE# low
level time will be promised to meet tWP_min and tWC_min requirement,
and RE# low level time will be promised to meet tREA_max, tRP_min and
tRC_min requirement.

Fixes: edfee361 ("mtd: nand: mtk: add ->setup_data_interface() hook")
Cc: stable@vger.kernel.org # v4.17+
Signed-off-by: NXiaolei Li <xiaolei.li@mediatek.com>
Reviewed-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

The way oobregion->offset is derived for large page NAND parts is
wrong, fixes it.

Fixes: ef5eeea6 ("mtd: nand: brcm: switch to mtd_ooblayout_ops")
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Used in several S5PV210-based Galaxy S devices, among them SGH-T959V,
SGH-T959P, SGH-T839, and SPH-D700.
Signed-off-by: NJonathan Bakker <xc-racer2@live.ca>
Signed-off-by: NPaweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

During probe, check the "get_irq" error value.
Signed-off-by: NFabien Dessenne <fabien.dessenne@st.com>
Acked-by: NChristophe Kerello <christophe.kerello@st.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Sometimes the exec_op parser does not choose the optimal pattern if
multiple patterns with optional elements are available. Since the stack
automatically splits operations in multiple exec_op calls, a non-optimal
pattern gets broken up into multiple calls. E.g. an OOB read using the
vf610 driver:
  nand: executing subop:
  nand:     ->CMD      [0x00]
  nand:     ->ADDR     [5 cyc: 00 08 ea 94 02]
  nand:     ->CMD      [0x30]
  nand:     ->WAITRDY  [max 200000 ms]
  nand:       DATA_IN  [64 B]
  nand: executing subop:
  nand:       CMD      [0x00]
  nand:       ADDR     [5 cyc: 00 08 ea 94 02]
  nand:       CMD      [0x30]
  nand:       WAITRDY  [max 200000 ms]
  nand:     ->DATA_IN  [64 B]

However, the vf610 driver has a pattern which can execute the complete
command in a single go...

This patch makes sure that the longest matching pattern is chosen
instead of the first (potentially only partial) match. With this
change the vf610 reads the OOB in a single exec_op call:
  nand: executing subop:
  nand:     ->CMD      [0x00]
  nand:     ->ADDR     [5 cyc: 00 08 c0 1d 00]
  nand:     ->CMD      [0x30]
  nand:     ->WAITRDY  [max 200000 ms]
  nand:     ->DATA_IN  [64 B]
Reported-by: NSascha Hauer <s.hauer@pengutronix.de>
Suggested-by: NBoris Brezillon <boris.brezillon@collabora.com>
Tested-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>

Pull x86 fixes from Ingo Molnar:
 "Two fixes: a quirk for KVM guests running on certain AMD CPUs, and a
  KASAN related build fix"

* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/CPU/AMD: Don't force the CPB cap when running under a hypervisor
  x86/boot: Provide KASAN compatible aliases for string routines