GEN8 now has a qword to code for 48bit addresses.
Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: NBen Widawsky <ben@bwidawsk.net>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

It seems like it wouldn't be too unlikely to be wanting to use a an
expression in the macro argument and things could go very wrong.
Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: NBen Widawsky <ben@bwidawsk.net>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Needs to happen after clock is running or it doesn't behave correctly.

v2: fix subject (Ville)
    make it clearer that this occurs in pre_enable (Paulo)
    misc bikesheds (Paulo)
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Allows sending of the null packets for conformance.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

We also do a disable later when we write a specific infoframe, but here
we do it to prevent sending a stale one before updating the infoframes.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

In case we end up bouncing these around between ports.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

We will have another use for the maximum watermark values that the
registers can hold. Pull those out into separate functions.
Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Even though the inactive pipes should have their watermarks set to all 0
with enable=true, we can possibly shave off a few cycles by completely
skipping the merge procedure for inactive pipes.
Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

intel_pipe_wm will be used to track the state in different stages
of the watermark update process. For that we need to keep a bit
more state in intel_pipe_wm.

We also need to separate the multi-pipe intel_wm_config computation
from ilk_compute_wm_parameters() as that one deals with the future
state, and we need the intel_wm_config to match the current hardware
state at the time we do the watermark merging for multiple pipes.
Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Frob conflict.]
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

As we've learned over time, the HW context is just a series of GPU
commands that we're able to decode without any changes in
intel_error_decode. Since many bugs recently have been implicated in
the HW context state, it makes sense to dump the whole context object
in a form which can be parsed.

Sample:
render ring --- HW Context = 0x042db000
ringbuffer (render ring) at 0x0160c000; HEAD points to: 0x0160c000
0x0160c000:      0x00000000: MI_NOOP
0x0160c004:      0x00000000: MI_NOOP
0x0160c008:      0x00000000: MI_NOOP
0x0160c00c:      0x00000000: MI_NOOP
0x0160c010:      0x00000000: MI_NOOP
0x0160c014:      0x00000000: MI_NOOP
0x0160c018:      0x00000000: MI_NOOP
0x0160c01c:      0x00000000: MI_NOOP

Unfortunately, our decoder isn't quite smart enough to deal with the
variable length LRIs - but that is a tools problem.
Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
[danvet: Clarify commit message a bit, seems to have lost a few
crucial words.]
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

This always indicates a bug somewhere.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

I opted to do this instead of grabbing the context reference after
eb_create since eb_create can potentially call the shrinker, and that
makes things very complicated. This simple patch balances the ref count
without requiring a great deal of review to make sure the shrinker path
is safe.

Theoretically (by design) the shrinker can end up destroying a context,
which enforces the reasoning for doing the fix this way instead of
moving the reference to later in the function.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Sprite LP2+ registers don't exist on ILK/SNB so don't read them.
Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

We don't do CPU access to GPU contexts so making the GPU access snoop
the CPU caches seems silly, and potentially expensive.

v2: Use !IS_VALLEYVIEW instead of HAS_LLC as this is really
    about what the PTEs can represent.
    Add a comment clarifying the situation.
Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

On Gen4+ platforms (except BDW), Render Cache Operational flush
cannot be enabled.
This WA is apparently required for all Gen4+ platforms,except BDW.
In BDW, the bit has been repurposed otherwise.
This has been tested only on vlv.

v2: Corrected the code regarding the wrong usage of
MASKED_BIT_DISABLE (Chris)

v3: Enhancing the scope of WA to Gen4+ platforms except BDW (Ville)

v4: Adding WA for g4x, crestline, broadwater (Ville)
Signed-off-by: NAkash Goel <akash.goel@intel.com>
Signed-off-by: NSourab Gupta <sourab.gupta@intel.com>
Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Loading cursors to the LCD controller's SRAM can be corrupted when the
configured pixel clock is relatively slow.  This seems to be caused
when we write back-to-back to the SRAM registers.

There doesn't appear to be any status register we can read to check
when an access has completed.

Inserting a dummy read between the writes appears to fix the problem.

Cc: <stable@vger.kernel.org> # 3.13
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NDave Airlie <airlied@redhat.com>

If we get a msg.reply of REPLY_DEFER, we also get an err of 0
so we fail reads with 0 < size and return -EPROTO instead of trying
again.

v2: same fix in i2c code.

Found writing MST support.
Reviewed-by: NJani Nikula <jani.nikula@intel.com>
Reviewed-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

This patch exports ptn3460_init function so that other modules
can call this function.
Signed-off-by: NInki Dae <inki.dae@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>

This patch removes MODULE_DEVICE_TABLE definition to of_device_id
of DP and MIPI-DSI drivers.

Eyxnos drm should be built as single module so these definitions
should be removed.
Signed-off-by: NInki Dae <inki.dae@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>

The patch adds MIPI-DSI based S6E8AA0 AMOLED LCD panel driver.
Driver uses mipi_dsi bus to communicate with panel and exposes drm_panel
interface.

v2
- added bus error handling,
- set maxmimum DSI packet size on init,
- removed unsupported brightness drm_panel callbacks,
- minor improvements

v3
- switched to gpiod framework,
- minor fixes in error handling
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

The patch adds LD9040 parallel RGB panel driver with SPI control interface.
The driver uses drm_panel framework.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

The patch adds driver for Exynos DSI master (DSIM). It is a platform driver
which is registered as exynos_drm_display sub-driver of exynos_drm framework
and implements DRM encoder/connector pair.
It is also MIPI-DSI host driver and provides DSI bus for panels.
It interacts with its panel(s) using drm_panel framework.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

This patch adds explicit check if there is a connector with
connected status before fbdev initialization. It prevents creation
of default fbdev 1024x768 which is unusable on panels with bigger resolutions.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

MIPI DSI host node can contain child nodes which are not DSI devices.
Checking for existence of reg property can be used to distinguish such nodes.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

The Dell XPS 8700 has a onboard Display port and HDMI port and no VGA port.
The call intel_crt_init freeze the machine, so skip such call.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73559
Signed-off-by: Giacomo Comes <comes at naic.edu>
Cc: stable@vger.kernel.org
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

This typo may lead to missed RPS interrupts and as a result a too
low or too high frequency for the current workload. The interrupt mask
will be set properly at a subsequent GPU idle event, but can get
corrupted again at the next RPS up/down event.
Signed-off-by: NImre Deak <imre.deak@intel.com>
Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

As per the inputs provided by hardware team  we still use DDR
Rates as 0,1=800, 2=1066, 3=1333.
With this change, Turbo freqs used on current machines matches.

This reverts commit f64a28a7.

commit f64a28a7
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date:   Mon Nov 4 16:07:00 2013 -0800

     drm/i915/vlv: fixup DDR freq detection per Punit spec

v2: Add reference to previous commit which changed this. (Daniel)
Acked-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NDeepak S <deepak.s@linux.intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

During resume the intel hda audio driver depends on the i915 driver
reinitializing the audio power domain. Since the order of calling the
i915 resume handler wrt. that of the audio driver is not guaranteed,
move the power domain reinitialization step to the resume_early
handler. This is guaranteed to run before the resume handler of any
other driver.

The power domain initialization in turn requires us to enable the i915
pci device first, so move that part earlier too.

Accordingly disabling of the i915 pci device should happen after the
audio suspend handler ran. So move the disabling later from the i915
resume handler to the resume_late handler.

v2:
- move intel_uncore_sanitize/early_sanitize earlier too, so they don't
  get reordered wrt. intel_power_domains_init_hw()

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76152Signed-off-by: NImre Deak <imre.deak@intel.com>
Reviewed-by: NTakashi Iwai <tiwai@suse.de>
Cc: stable@vger.kernel.org
[danvet: Add cc: stable and loud comments that this is just a hack.]
[danvet: Fix "Should it be static?" sparse warning reported by Wu
Fengguang's kbuilder.]
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Use the more canonical and concise variant of the GPL v2 license text.
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The majority of the code in this driver is licensed under the GPL v2, so
relicense the rest under GPL v2 as well for consistency.
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add support for eDP functionality found on Tegra124 and later SoCs. Only
fast link training is currently supported.
Signed-off-by: NThierry Reding <treding@nvidia.com>

This is trivial to support since all GEM objects are mapped into kernel
space anyway.
Signed-off-by: NThierry Reding <treding@nvidia.com>

This panel is used by Tegra Note 7 and supported by the simple-panel
driver.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This panel is used by the NVIDIA SHIELD and supported by the
simple-panel driver.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

In order to differentiate between the different video modes (burst vs.
non-burst, sync pulses vs. sync events) supported by peripherals, pass
the flags that specify this mode in the panel description to the DSI
peripheral device when probed.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The enable GPIO for panels may be provided by GPIO expanders on slow
busses (such as I2C), and therefore toggling the GPIO may sleep. Since
these accesses don't happen in interrupt context, use the *_cansleep()
variants of the GPIO API.
Signed-off-by: NThierry Reding <treding@nvidia.com>

regulator_disable() is already performed by panel_simple_disable(),
which is called by panel_simple_remove().
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Use the new GPIO descriptor interface to handle the panel's enable GPIO.
This considerably simplifies the code.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
[treding@nvidia.com: rework to improve readability]
Signed-off-by: NThierry Reding <treding@nvidia.com>

The LP129QE LCD has an LED backlight and a display resolution of
2560x1700 pixels.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Signed-off-by: NThomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: NBrian Paul <brianp@vmware.com>