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  1. 17 10月, 2015 4 次提交
  3. 16 10月, 2015 1 次提交
    • S
      clk: Make of_clk_get_parent_name() robust with #clock-cells = 1 · 0a4807c2
      由 Stephen Boyd 提交于 
      If a clock provider has #clock-cells = 1 and we call
of_clk_get_parent_name() on it we may end up returning the name
of the provider node if the provider doesn't have a
clock-output-names property. This doesn't make sense, especially
when you consider that calling of_clk_get_parent_name() on such a
node with different indices will return the same name each time.

Let's try getting the clock from the framework via of_clk_get()
instead, and only fallback to the node name if we have a provider
with #clock-cells = 0. This way, we can't hand out the same name
for different clocks when we don't actually know their names.

Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      0a4807c2
  5. 15 10月, 2015 2 次提交
  7. 13 10月, 2015 2 次提交
    • J
      clk: tegra: delete unneeded of_node_put · 4e4f485c
      由 Julia Lawall 提交于 
      for_each_child_of_node performs an of_node_put on each iteration, so
putting an of_node_put before a continue results in a double put.

The semantic match that finds this problem is as follows
(http://coccinelle.lip6.fr):

// <smpl>
@@
expression root,e;
local idexpression child;
iterator name for_each_child_of_node;
@@

 for_each_child_of_node(root, child) {
   ... when != of_node_get(child)
*  of_node_put(child);
   ...
*  continue;
}
// </smpl>
Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      4e4f485c
    • E
      clk: bcm2835: Add support for programming the audio domain clocks · 41691b88
      由 Eric Anholt 提交于 
      This adds support for enabling, disabling, and setting the rate of the
audio domain clocks.  It will be necessary for setting the pixel clock
for HDMI in the VC4 driver and let us write a cpufreq driver.  It will
also improve compatibility with user changes to the firmware's
config.txt, since our previous fixed clocks are unaware of it.

The firmware also has support for configuring the clocks through the
mailbox channel, but the pixel clock setup by the firmware doesn't
work, and it's Raspberry Pi specific anyway.  The only conflicts we
should have with the firmware would be if we made firmware calls that
result in clock management (like opening firmware V3D or ISP access,
which we don't support in upstream), or on hardware over-thermal or
under-voltage (when the firmware would rewrite PLLB to take the ARM
out of overclock).  If that happens, our cached .recalc_rate() results
would be incorrect, but that's no worse than our current state where
we used fixed clocks.

The existing fixed clocks in the code are left in place to provide
backwards compatibility with old device tree files.
Signed-off-by: NEric Anholt <eric@anholt.net>
Tested-by: NMartin Sperl <kernel@martin.sperl.org>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      41691b88
  9. 12 10月, 2015 1 次提交
    • S
      clk: imx6: Add SPDIF_GCLK clock in clock tree · 84a87250
      由 Shengjiu Wang 提交于 
      Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
one clock of SPDIF, which is missed before.

We found an issue that imx can't enter low power mode with spdif
if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
so its parent clock (PLL clock) is prepared, the prepare operation of
PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
then it can enter low power mode.

So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
SPDIF_GCLK's parent clock is ipg clock.
Signed-off-by: NShengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>
      84a87250
  11. 09 10月, 2015 11 次提交
  13. 03 10月, 2015 6 次提交
  15. 02 10月, 2015 13 次提交