As PHYS_OFFSET will be becoming a variable, we can't have it used in
initializers nor assembly code.  Replace those in generic code with
a run-time initialization.  Replace those in platform code using the
individual platform specific PLAT_PHYS_OFFSET.
Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Acked-by: NDavid Brown <davidb@codeaurora.org>
Acked-by: NEric Miao <eric.y.miao@gmail.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This uncouple PHYS_OFFSET from the platform definitions, thereby
facilitating run-time computation of the physical memory offset.
Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: NViresh Kumar <viresh.kumar@st.com>
Acked-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NWan ZongShun <mcuos.com@gmail.com>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Acked-by: NEric Miao <eric.y.miao@gmail.com>
Acked-by: NJiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NLennert Buytenhek <buytenh@secretlab.ca>
Acked-by: NGregory Bean <gbean@codeaurora.org>
Acked-by: NDaniel Walker <dwalker@codeaurora.org>

Signed-off-by: NJeff Ohlstein <johlstei@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Signed-off-by: NJeff Ohlstein <johlstei@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

The msm provides timer hardware that is private to each core. Each
timer has separate counter and match registers, so we create separate
clock_event_devices for each core. For the global clocksource, use
cpu 0's counter.
Signed-off-by: NJeff Ohlstein <johlstei@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Add support for setting the cold boot address of core 1 and
the warm boot addresses of cores 0 and 1 using a secure
domain call.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

SCM is the protocol used to communicate between the secure and
non-secure code executing on the applications processor. The
non-secure side uses a physically contiguous buffer to pass
information to the secure side; where the buffer conforms to a
format that is agreed upon by both sides. The use of a buffer
allows multiple pending requests to be in flight on the secure
side. It also benefits use cases where the command or response
buffer contains large chunks of data.
Reviewed-by: NSaravana Kannan <skannan@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

In d7e81c26 (clocksource: Add clocksource_register_hz/khz interface) new
interfaces were added which simplify (and optimize) the selection of the
divisor shift/mult constants.  Switch over to using this new interface.
Tested-By: NJeff Ohlstein <johlstei@codeaurora.org>
Acked-by: NDavid Brown <davidb@codeaurora.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Remove the SMC91x platform and resource data from initdata.  These
will continue to be accessed after init, and must remain available.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Add USB OTG, peripheral and host devices.  This patch also adds
usb_phy_clk which is required for resetting the PHY.  VBUS power up
and shutdown routines depends on PMIC module.  As PMIC driver is
unavailable, configure USB in peripheral only mode.
Signed-off-by: NPavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

OTG driver takes care of putting hardware into low power mode.  Hence
make peripheral and host devices as children of OTG device and let
runtime PM takes care of notifying peripheral and host state to
OTG device.  VBUS power up and shutdown routines are implemented by
modem processor.  As RPC infrastructure is not available, configure
USB in peripheral only mode.
Signed-off-by: NPavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Initial framebuffer components. Add board-trout-panel.c
as well as platform parts to enable the framebuffer. This
code comes directly from Google's tree.
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

CLK_MINMAX is used to denote clocks that have a wide variation
in possible frequencies. This handling just sets the min and
max values to the same value.
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

This clock is used in the framebuffer driver as mddi_clk.
This just changes the name to match that. This also
mirrors a change in Google tree.
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

This adds in the CLK_MINMAX flag to the pmdh_clk since it's actual
a min/max clock instead of a single frequency clock.
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

trout has gpiolib support and interrupt support, but was
missing the gpio_to_irq function. This adds that functions
which should allow proper translation.
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Change msm_iommu_map to use GFP_ATOMIC instead of
GFP_KERNEL due to the fact that the call occurs within
a spinlock-protected region.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>

Every architecture using the GIC has a gic_cpu_base_addr pointer for
GIC 0 for their entry assembly code to use to decode the cause of the
current interrupt.  Move this into the common GIC code.
Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
Tested-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Provide gic_init() which initializes the GIC distributor and current
CPU's GIC interface for the boot (or single) CPU.
Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
Tested-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NJiri Kosina <jkosina@suse.cz>

This allows us to use smp_cross_call() to trigger a number of different
software generated interrupts, rather than combining them all on one
SGI.  Recover the SGI number via do_IPI.
Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Remove some unneeded assignments and messages, restructure
a failure path in iova_to_phys, and make __flush_iotlb
return int in preparation for adding IOMMU clock control.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Add support for allowing IOMMU memory transactions to be
cache coherent, eliminating the need for software cache
management in certain situations. This can lead to
improvements in performance and power usage, assuming the
multimedia core's access pattern exhibits spatial locality
and that its working set fits into the cache.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Add the register field definitions and memory attribute
definitions that will be needed to support IOMMU
transactions with cache-coherent memory access.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Make the IOMMU driver select the IOMMU API in the kernel
configuration.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

An IOMMU device can only be attached to one IOMMU domain at
any given time. Check whether the device is already
attached to a domain before allowing it to be attached to
another domain. If so, return busy.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Add a Kconfig item to allow the IOMMU page tables to be
coherent in the L2 cache. This generally reduces IOTLB miss
latencies and has been shown to improve multimedia
performance.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Don't flush the page tables on an IOMMU domain if there are
no IOMMU devices attached to the domain. The act of
attaching to the domain will cause an implicit flush of
those areas if the page tables are configured to not be L2
cacheable.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Mark the init and exit functions as __init and __exit where
appropriate.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Add the platform data and resources needed for the second
2D graphics core's IOMMU.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Based on recommendations from chip designers,
optimize the Machine ID to translation context
mappings for the first 2D core's IOMMU. Remove the
"gfx2d0_texv3_smmu" context, as it is no longer needed
under the new mapping scheme.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Based on recommendations from chip designers,
optimize the Machine ID to translation context
mappings for the 3D core's IOMMU. Remove the
the "gfx3d_smmu" context device, as it is no longer
needed under the new mapping scheme.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
[dwalker@codeaurora.org: updated commit text]
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Rename all the IOMMU platform devices so that the names are
more consistent with the rest of the codebase.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Add register addresses and IRQ numbers for the IOMMU used
for the second 2D graphics core.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

On msm8x60, the MID field on the AXI connection to the
IOMMU can be up to five bits wide. Thus, allow the IOMMU
context platform data to map up to 32 MIDs.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Complete the MSM v2 gpio subsystem by adding irq_chip.
Signed-off-by: NGregory Bean <gbean@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Beginning with the MSM8x60, the hardware block responsible for gpio
support changes.  Provide gpiolib support for the new v2 architecture.

Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Pavan Kondeti <pkondeti@codeaurora.org>
Signed-off-by: NGregory Bean <gbean@codeaurora.org>
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

This just adds ARCH_MSM_SCORPIONMP to allow SMP selection for
MSM. MSM is unique in that it doesn't enable SCU or TWD.
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Commit 7c63984b (ARM: do not define VMALLOC_END relative to PAGE_OFFSET)
changed VMALLOC_END to be an explicit value. Before this, it was
relative to PAGE_OFFSET and therefore converted to unsigned long
as PAGE_OFFSET is an unsigned long. This introduced the following
build warning. Fix this by changing the explicit defines of
VMALLOC_END to be unsigned long.

  CC      arch/arm/mm/init.o
arch/arm/mm/init.c: In function 'mem_init':
arch/arm/mm/init.c:606: warning: format '%08lx' expects type 'long unsigned int', but argument 12 has type 'unsigned int'
Signed-off-by: NAnand Gadiyar <gadiyar@ti.com>
Acked-by: NUwe Kleine-K <u.kleine-koenig@pengutronix.dee>
Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>