In the patch sent by Daniel Drake under the title "[PATCH] ieee80211: Move
IV/ICV stripping into ieee80211_rx", a needed line was accidentally removed.

(NOTE: I'm pretty sure this was my fault, not Daniel's. -- JWL)
Signed-off-by: NLarry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

This reverts commit 477c517903d57047150b01608149e02c6e9d83dd.

This patch depended on something that was not yet committed.

Driver for the Atmel MACB on-chip ethernet module.

Tested on AVR32/AT32AP7000/ATSTK1000. I've heard rumours that it works
with AT91SAM9260 as well, and it may be possible to share some code with
the at91_ether driver for AT91RM9200.

Hardware documentation can be found in the AT32AP7000 data sheet,
which can be downloaded from

http://www.atmel.com/dyn/products/datasheets.asp?family_id=682

Changes since previous version:
  * Probe for PHY ID instead of depending on it being provided through
    platform_data.
  * Grab initial ethernet address from the MACB registers instead
    of depending on platform_data.
  * Set MII/RMII mode correctly.

These changes are mostly about making the driver more compatible with
the at91 infrastructure.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Another thing, reported recently to me by several people - DSCC4 WAN
driver now (and perhaps for the last couple of years+) requires the
generic HDLC. I've fixed the Kconfig and moved the DSCC4 option
under CONFIG_HDLC so it's consistent visually.
Signed-off-by: NKrzysztof Halasa <khc@pm.waw.pl>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Add tsi108/9 on chip Ethernet controller driver support.

The driver code collects the feedback of previous posting form the mailing
list and gives the update.

MPC7448HPC2 platform in arch/powerpc uses tsi108 bridge.

The following is a brief description of the Ethernet controller:

The Tsi108/9 Ethernet Controller connects Switch Fabric to two independent
Gigabit Ethernet ports,E0 and E1.  It uses a single Management interface to
manage the two physical connection devices (PHYs).  Each Ethernet port has
its own statistics monitor that tracks and reports key interface
statistics.  Each port supports a 256-entry hash table for address
filtering.  In addition, each port is bridged to the Switch Fabric through
a 2-Kbyte transmit FIFO and a 4-Kbyte Receive FIFO.

Each Ethernet port also has a pair of internal Ethernet DMA channels to
support the transmit and receive data flows.  The Ethernet DMA channels use
descriptors set up in memory, the memory map of the device, and access via
the Switch Fabric.  The Ethernet Controller’s DMA arbiter handles
arbitration for the Switch Fabric.  The Controller also has a register bus
interface for register accesses and status monitor control.

The PMD (Physical Media Device) interface operates in MII, GMII, or TBI
modes.  The MII mode is used for connecting with 10 or 100 Mbit/s PMDs.
The GMII and TBI modes are used to connect with Gigabit PMDs.  Internal
data flows to and from the Ethernet Controller through the Switch Fabric.
Each

Ethernet port uses its transmit and receive DMA channels to manage data
flows through buffer descriptors that are predefined by the system (the
descriptors can exist anywhere in the system memory map).  These
descriptors are data structures that point to buffers filled with data
ready to transmit over Ethernet, or they point to empty buffers ready to
receive data from Ethernet.
Signed-off-by: NAlexandre Bounine <Alexandre.Bounine@tundra.com>
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

[PATCH] sundance: solve host error problem in low performance embedded system when continune down and up

Solve host error problem in low performance embedded system when continune
down and up.  It will cause IP100A DMA TargetAbort.  So we need more safe
process to up and down IP100A with wait hardware completely stop and software
cur_tx/ dirty_tx/cur_task/last_tx be clear.
Signed-off-by: NJesse Huang <jesse@icplus.com.tw>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

ia64:

 drivers/built-in.o(.text+0xd9a72): In function `e1000_xmit_frame':
 : undefined reference to `csum_ipv6_magic'

Cc: Auke Kok <auke-jan.h.kok@intel.com>
Cc: "David S. Miller" <davem@davemloft.net>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

This patch requires the new support for configurable PHY
interfaces.

Changes include:
* New support for 88e1145
* New support for 88e111s
* Fixing 88e1101 driver to not match non-88e1101 PHYs
* Increases in feature support across Marvell PHY product line
* Fixes a bunch of whitespace issues found by Lindent
Signed-off-by: NAndrew Fleming <afleming@freescale.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

The patch inlined below adds NET_POLL_CONTROLLER support for gianfar network driver, slightly modified wrt the comments from Andy Fleming.

 drivers/net/gianfar.c |   33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
Signed-off-by: NVitaly Wool <vwool@ru.mvista.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Clean-up some warnings from missing return code checks, mostly from
calling pci_enable_device during a PCI resume.
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

SoftMAC contains a number of debug-type messages that continue to print
even when debugging is turned off. This patch substitutes dprintkl for
printkl for those lines.
Signed-off-by: NLarry Finger <Larry.Finger@lwfinger.net>
Acked-by: NJohannes Berg <johannes@sipsolutions.net>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

In the softmac version of bcm43xx, the core scan logs whether each core is
enabled or disabled. This information is useless as one of the next steps
is to enable all cores. This patch removes this output from the log.
Signed-off-by: NLarry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

When the periodic work function in bcm43xx was converted for voluntary preemption
to reduce latency, a new function was created to estimate the "badness" of
each step, and this quantity was used to determine if preemption should be
enabled when periodic work was undertaken. This concept was quite useful
while debugging of periodic work was in progress. Now that this routine
seems to be working correctly, it is time to simplify the code. This
patch keeps the functionality intact, but simplifies the code.
Signed-off-by: NLarry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

Most contributed and Signed-off-by: Andrew Morton <akpm@osdl.org>
with some from me as well.
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Correct initial and close hardware step.  In some embedded system down and up
IP100A will cause DMA crash.  We add some for safe down and up IP100A.
Signed-off-by: NJesse Huang <jesse@icplus.com.tw>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

* genphy_update_link is now exported
* Added a fix from ncase@xes-inc.com which changes forcing so it
  only updates the link.  Otherwise, it never tries the lower
  values, since it is always overwriting the speed/duplex values
  with the current ones, rather than the intended ones.
* Fixed a bug where bringing up a PHY with no link caused it to
  timeout, and enter forcing mode.  Once in forcing mode,
  plugging in the link didn't autonegotiate.  Now the AN state
  detects the lack of link, and enters the NO_LINK state.  AN
  only times out if the link is up and AN fails
* Cleaned up the PHY_AN case, reducing one level of indentation
  for the timeout code.
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Fix TX Pause bug (reset_tx, intr_handler).  When MaxCollisions occurred, need
to re-enable Tx.  But just after re-enable, MaxCollisions maybe occurred again
and with TxStatusOverflow.  This will cause driver can't check new
MaxCollisions to re-enable Tx again, because TxStatusOverflow.  For this
reason, after re-enable Tx, we need to make sure Tx was actually enabled.
Signed-off-by: NJesse Huang <jesse@icplus.com.tw>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

For patent issue need to remove TxStartThresh and RxEarlyThresh.  This patent
is cut-through patent.  If use this function, Tx will start to transmit after
few data be move in to Tx FIFO.  We are not allow to use those function in
DFE530/DFE550/DFE580/DL10050/IP100/IP100A.  It will decrease a little
performance.
Signed-off-by: NJesse Huang <jesse@icplus.com.tw>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Remove the code to change the E8390_CMD register from ei_watchdog().
The 8390-page is always 0 outside the spin_lock.

Signed-off-by: komurojun-mbn@nifty.com
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Add support for the new mcp67 device into forcedeth.
Signed-off-by: NAyaz Abdulla <aabdulla@nvidia.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Add pci device ids for the NVIDIA MCP67 chip.
Signed-off-by: NAyaz Abdulla <aabdulla@nvidia.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

This patch adds support to recover from a previously fatal MAC error. In
the past the MAC would be hung on an internal fatal error. On new
chipsets, the MAC has the ability to enter a non-fatal state and allow
the driver to re-init it.
Signed-Off-By: NAyaz Abdulla <aabdulla@nvidia.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

This patch adds support for the mgmt unit in certain chipsets. The MAC
and the mgmt unit share the PHY and therefore proper intialization
procedures are needed for them to maintain coexistense.
Signed-Off-By: NAyaz Abdulla <aabdulla@nvidia.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

 The PDQ DMA engine requires a different byte-swapping mode for big-endian
hosts; also the MAC address which is read from a register through PIO has
to be byte-swapped.  These changes have been verified with DEFPA-DC (PCI)
boards and a Broadcom BCM91250A (MIPS CPU based) host.
Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

hi,

replace open coded kmemdup() to save some screen space,
and allow inlining/not inlining to be triggered by gcc.
Signed-off-by: NEric Sesterhenn <snakebyte@gmx.de>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Realtek's 8139/810x (0x8136) PCI-E comes with a touchy PHY.
A big heavy reset seems to calm it down.

Fix for http://bugzilla.kernel.org/show_bug.cgi?id=7378.
Signed-off-by: NFrancois Romieu <romieu@fr.zoreil.com>
Signed-off-by: NDarren Salt <linux@youmustbejoking.demon.co.uk>

Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Add a new dynamic itr algorithm, with 2 modes, and make it the default
operation mode. This greatly reduces latency and increases small packet
performance, at the "cost" of some CPU utilization. Bulk traffic
throughput is unaffected.

The driver can limit the amount of interrupts per second that the
adapter will generate for incoming packets. It does this by writing a
value to the adapter that is based on the maximum amount of interrupts
that the adapter will generate per second.

Setting InterruptThrottleRate to a value greater or equal to 100 will
program the adapter to send out a maximum of that many interrupts per
second, even if more packets have come in. This reduces interrupt
load on the system and can lower CPU utilization under heavy load,
but will increase latency as packets are not processed as quickly.

The default behaviour of the driver previously assumed a static
InterruptThrottleRate value of 8000, providing a good fallback value
for all traffic types,but lacking in small packet performance and
latency. The hardware can handle many more small packets per second
however, and for this reason an adaptive interrupt moderation algorithm
was implemented.

Since 7.3.x, the driver has two adaptive modes (setting 1 or 3) in
which it dynamically adjusts the InterruptThrottleRate value based on
the traffic that it receives. After determining the type of incoming
traffic in the last timeframe, it will adjust the InterruptThrottleRate
to an appropriate value for that traffic.

The algorithm classifies the incoming traffic every interval into
classes.  Once the class is determined, the InterruptThrottleRate
value is adjusted to suit that traffic type the best. There are
three classes defined: "Bulk traffic", for large amounts of packets
of normal size; "Low latency", for small amounts of traffic and/or
a significant percentage of small packets; and "Lowest latency",
for almost completely small packets or minimal traffic.

In dynamic conservative mode, the InterruptThrottleRate value is
set to 4000 for traffic that falls in class "Bulk traffic". If
traffic falls in the "Low latency" or "Lowest latency" class, the
InterruptThrottleRate is increased stepwise to 20000. This default
mode is suitable for most applications.

For situations where low latency is vital such as cluster or
grid computing, the algorithm can reduce latency even more when
InterruptThrottleRate is set to mode 1. In this mode, which operates
the same as mode 3, the InterruptThrottleRate will be increased
stepwise to 70000 for traffic in class "Lowest latency".

Setting InterruptThrottleRate to 0 turns off any interrupt moderation
and may improve small packet latency, but is generally not suitable
for bulk throughput traffic.
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Cc: Rick Jones <rick.jones2@hp.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Add a generic MSI interrupt routine that is IO read-free, speeding up
MSI interrupt handling.
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

This file needs some cleanups and reordering - logically order it
so that relevant defines and code are together with properly quoted
defaults.
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Spec fix: don't set IDE unless we are actually setting the tx
int delay time.
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>

ICH8 will soon be followed by newer chipsets bearing the same acronym,
thus we remove the '8' and make it independent of the version number in
the platform name.
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Add a netif_wake/start_queue counter to the ethtool statistics to indicated
to the user that their transmit ring could be too small for their workload.
Signed-off-by: NJesse brandeburg <jesse.brandeburg@intel.com>
Cc: Jamal Hadi <hadi@cyberus.ca>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Add support for a Low Profile quad-port PCI-E adapter and 2 variants
of the ICH8 systems' onboard NIC's.
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

This memsetting was added in a paranoid rage debugging TX hangs, but
are no longer of importance. We can beef up the performance quite a
bit removing them. Make sure to fill in next_to_watch to allow this.
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>

Simplify two calls to skb_put by removing one call to it.
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Order pci-e capability struct according to bus/pci bus width ordering
preserving the hard pci spec numbers.
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

On ich systems during PHY power down to D3, the voltage regulators
were left on.
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

IA64 SMP systems were seeing TX issues with multiple cpu's attempting
to write tail registers unordered. This mmiowb() fixes the issue.
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>