1. 19 9月, 2013 5 次提交
    • A
      ARM: OMAP4 SMP: Corrected a typo fucntions to functions · b6b24852
      Anoop Thomas Mathew 提交于
      Corrected the functions spelling mistake in the OMAP4 SMP source file.
      Signed-off-by: NAnoop Thomas Mathew <atm@profoundis.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      b6b24852
    • V
      ARM: OMAP4: cpuidle: fix: call cpu_cluster_pm_exit conditionally · 78350271
      Vladimir Murzin 提交于
      We call cpu_cluster_pm_enter for dev->cpu == 0 only, but
      cpu_cluster_pm_exit called without that check.
      
      Because of that unhandled page fault may happen:
      
      [    3.803405] Unable to handle kernel paging request at virtual address 00002500
      [    3.810974] pgd = c0004000
      [    3.813812] [00002500] *pgd=00000000
      [    3.817596] Internal error: Oops: 5 [#1] SMP ARM
      [    3.822418] Modules linked in:
      [    3.825653] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 3.11.0-rc6+ #21
      [    3.832397] task: ed86ef40 ti: ed896000 task.ti: ed896000
      [    3.838073] PC is at irq_notifier+0x234/0x25c
      [    3.842651] LR is at irq_notifier+0x218/0x25c
      [    3.847229] pc : [<c0029ed8>]    lr : [<c0029ebc>]    psr: 80000193
      [    3.847229] sp : ed897ee8  ip : 00000005  fp : 00000001
      [    3.859283] r10: c0b395f0  r9 : c0b30594  r8 : c0b8c2ac
      [    3.864776] r7 : ffffffff  r6 : 00000000  r5 : 00000005  r4 : 00000000
      [    3.871643] r3 : 00002500  r2 : 00000000  r1 : 00000005  r0 : 44302244
      [    3.878479] Flags: Nzcv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
      [    3.886260] Control: 10c5387d  Table: 8000404a  DAC: 00000015
      [    3.892272] Process swapper/1 (pid: 0, stack limit = 0xed896240)
      [    3.898590] Stack: (0xed897ee8 to 0xed898000)
      [    3.903167] 7ee0:                   c0979c3a 00000001 ed897ef8 ed896000 c0014f7c 00000000
      [    3.911743] 7f00: 00000005 00000000 ffffffff c0b8c2ac c0b395f0 c077c04c c0c94b48 c0b3953c
      [    3.920318] 7f20: c0bcd928 00000002 c0b39524 c00cfad8 00000000 ffffffff 00000000 c00cfb10
      [    3.928924] 7f40: c14e62c0 c002c1c8 c002c0ac c14e62c0 00000002 e251c37d 00000000 c0b39548
      [    3.937499] 7f60: c0b395f0 c05a1bc4 e251c37d 00000000 00000005 c05a3870 edc90380 edc90380
      [    3.946105] 7f80: edc90394 c14e62c0 c0b39548 00000002 c0784064 c05a3c78 c0b395e0 c14e62c0
      [    3.954681] 7fa0: 00000002 c0b39548 c0bc9db8 00000000 00000001 c05a1dc0 ed896000 00000015
      [    3.963287] 7fc0: c0bc9db8 ed896000 8000406a c0b30594 c0784064 c000e504 00000746 c007a528
      [    3.971862] 7fe0: 00000001 0000001d 600001d3 c0bcc004 00000000 800086c4 ee0aa6a7 d2aabaa9
      [    3.980499] [<c0029ed8>] (irq_notifier+0x234/0x25c) from [<c077c04c>] (notifier_call_chain+0x38/0x68)
      [    3.990173] [<c077c04c>] (notifier_call_chain+0x38/0x68) from [<c00cfad8>] (cpu_pm_notify+0x20/0x38)
      [    3.999786] [<c00cfad8>] (cpu_pm_notify+0x20/0x38) from [<c00cfb10>] (cpu_cluster_pm_exit+0x20/0x50)
      [    4.009399] [<c00cfb10>] (cpu_cluster_pm_exit+0x20/0x50) from [<c002c1c8>] (omap_enter_idle_coupled+0x11c/0x14c)
      [    4.020111] [<c002c1c8>] (omap_enter_idle_coupled+0x11c/0x14c) from [<c05a1bc4>] (cpuidle_enter_state+0x40/0xec)
      [    4.030822] [<c05a1bc4>] (cpuidle_enter_state+0x40/0xec) from [<c05a3c78>] (cpuidle_enter_state_coupled+0x1f4/0x240)
      [    4.041870] [<c05a3c78>] (cpuidle_enter_state_coupled+0x1f4/0x240) from [<c05a1dc0>] (cpuidle_idle_call+0x150/0x228)
      [    4.052947] [<c05a1dc0>] (cpuidle_idle_call+0x150/0x228) from [<c000e504>] (arch_cpu_idle+0x8/0x38)
      [    4.062499] [<c000e504>] (arch_cpu_idle+0x8/0x38) from [<c007a528>] (cpu_startup_entry+0x178/0x1e4)
      [    4.071990] [<c007a528>] (cpu_startup_entry+0x178/0x1e4) from [<800086c4>] (0x800086c4)
      [    4.080383] Code: e5922288 03a03b0a 13a03c25 e0823003 (e5932000)
      [    4.086791] ---[ end trace d83954a84a6fa69e ]---
      
      It is supposed that sar_base is initialized in irq_save_context, which
      is called on CPU_CLUSTER_PM_ENTER notification. If this notification
      has been missed and CPU_CLUSTER_PM_EXIT is received sar_base is NULL.
      
      Fix it by calling CPU_CLUSTER_PM_{ENTER,EXIT} under the same condition.
      Signed-off-by: NVladimir Murzin <murzin.v@gmail.com>
      Acked-by: NKevin Hilman <khilman@linaro.org>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      78350271
    • F
      ARM: mach-omap2: gpmc: Fix warning when CONFIG_ARM_LPAE=y · f70bf2a3
      Fabio Estevam 提交于
      When CONFIG_ARM_LPAE=y the following build warning is generated:
      
      arch/arm/mach-omap2/gpmc.c:1495:4: warning: format '%x' expects argument of type 'unsigned int', but argument 4 has type 'resource_size_t' [-Wformat]
      
      According to Documentation/printk-formats.txt '%pa' can be used to properly
      print 'resource_size_t'.
      Reported-by: NKevin Hilman <khilman@linaro.org>
      Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
      Acked-by: NKevin Hilman <khilman@linaro.org>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      f70bf2a3
    • W
      ARM: OMAP: fix return value check in omap_device_build_from_dt() · 4cf9cf89
      Wei Yongjun 提交于
      In case of error, the function omap_device_alloc() returns ERR_PTR()
      and never returns NULL. The NULL test in the return value check
      should be replaced with IS_ERR().
      Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
      Acked-by: NKevin Hilman <khilman@linaro.org>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      4cf9cf89
    • T
      ARM: OMAP4: Fix clock_get error for GPMC during boot · 2cfeed31
      Tony Lindgren 提交于
      Looks like we still have the legacy clock alias name for
      omap4 GPMC (General Purpose Memory Controller), so let's
      fix it for the device tree naming. There's no need to keep
      the legacy naming as omap4 is DT only nowadays.
      
      Without this fix we get the following error while booting:
      
      [    0.440399] omap-gpmc 50000000.gpmc: error: clk_get
      Reported-by: NOlof Johansson <olof@lixom.net>
      Cc: stable@vger.kernel.org # v3.11
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      2cfeed31
  2. 30 8月, 2013 2 次提交
  3. 29 8月, 2013 1 次提交
    • T
      OMAPDSS: fix DPI and SDI device ids · 35f5df6f
      Tomi Valkeinen 提交于
      The DPI and SDI platform devices are currently created with the ID of
      -1. The ID doesn't currently affect anything.
      
      However, we have added regulator supply entries for "omapdss_dpi.0" and
      "omapdss_sdi.0" to the board files, although these supply entries are
      not yet used. As the ID used for the devices is -1, these regulator
      supply entries will not work.
      
      To fix the issue, assign ID of 0 to the devices. In the future there may
      be more than one DPI or SDI output, so it makes sense to have a proper
      ID for them.
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      Reviewed-by: NArchit Taneja <archit@ti.com>
      35f5df6f
  4. 28 8月, 2013 18 次提交
  5. 24 8月, 2013 1 次提交
  6. 23 8月, 2013 13 次提交
    • A
      ARM: OMAP: TI81XX: add always-on powerdomain for TI81XX · 0f0dd089
      Aida Mynzhasova 提交于
      This patch adds alwon powerdomain support for TI81XX, which is required
      for stable functioning of a big number of TI81XX subsystems.
      Signed-off-by: NAida Mynzhasova <aida.mynzhasova@skitlab.ru>
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      0f0dd089
    • R
      ARM: OMAP4: clock: Lock PLLs in the right sequence · eeb6603f
      Rajendra Nayak 提交于
      On OMAP4 we have clk_set_rate()s being done for a few
      DPLL clock nodes, as part of the clock init code, since
      the bootloaders no longer locks these DPLLs.
      
      So we have a clk_set_rate() done for a ABE DPLL node (which
      inturn locks it) followed by a clk_set_rate() for the USB DPLL.
      
      With USB DPLL being in bypass, we have this parent->child
      relationship thats formed while the clocks get registered.
      
      dpll_abe_ck
          |
          V
      dpll_abe_x2_ck
          |
          V
      dpll_abe_m3x2_ck
          |
          V
      usb_hs_clk_div_ck
          |
          V
      dpll_usb_ck
      
      This is because usb_hs_clk_div_ck is bypass clock for dpll_usb_ck.
      
      So with this parent->child relationship in place, a clk_set_rate()
      on ABE DPLL results eventually in a clk_set_rate() call on USB DPLL,
      because CCF does a clk_change_rate() (as part of clk_set_rate()) on
      all downstream clocks resulting from a rate change on the top clock.
      
      So its important that we lock USB DPLL before we lock ABE DPLL.
      Without which we see these error logs at boot.
      [These error logs will not be seen if using a bootloader that locks
      USB DPLL]
      
      [    0.000000] clock: dpll_usb_ck failed transition to 'locked'
      [    0.000000] Division by zero in kernel.
      [    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af002-dirty #7
      [    0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
      [    0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
      [    0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
      [    0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
      [    0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
      [    0.000000] Division by zero in kernel.
      [    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af002-dirty #7
      [    0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
      [    0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
      [    0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
      [    0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
      [    0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
      [    0.000000] Division by zero in kernel.
      [    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af002-dirty #7
      [    0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
      [    0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
      [    0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
      [    0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
      [    0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
      [    0.000000] Division by zero in kernel.
      [    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af002-dirty #7
      [    0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
      [    0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
      [    0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
      [    0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
      [    0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
      [    0.000000] Division by zero in kernel.
      [    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af002-dirty #7
      [    0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
      [    0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
      [    0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
      [    0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
      [    0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
      [    0.000000] Division by zero in kernel.
      [    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af002-dirty #7
      [    0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
      [    0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
      [    0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
      [    0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
      [    0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
      [    0.000000] clock: trace_clk_div_ck: could not find divisor for target rate 0 for parent pmd_trace_clk_mux_ck
      [    0.000000] Division by zero in kernel.
      Signed-off-by: NRajendra Nayak <rnayak@ti.com>
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      eeb6603f
    • V
      ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSS · 1721c702
      Vaibhav Hiremath 提交于
      In the original hwmod data file, DebugSS entry was disabled,
      since we didn't (and do not) have SW to control it.
      
      This patch enables it back with right data, so that it can be
      controlled by different ways; and the suggested method it to
      have modular driver for debugSS as well.
      
      Refer to the link for more discussion on handling of debugSS -
      https://patchwork.kernel.org/patch/2212111/Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Tony Lindgren <tony@atomide.com>
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      1721c702
    • J
      ARM: OMAP2+: Only write the sysconfig on idle when necessary · 127500cc
      Jon Hunter 提交于
      Currently, whenever we idle a device _idle_sysc() is called and writes to the
      devices SYSCONFIG register to set the idle mode. A lot devices are using the
      smart-idle mode and so the write to the SYSCONFIG register is programming the
      same value that is already stored in the register.
      
      Writes to the devices SYSCONFIG register can be slow, for example, writing to
      the DMTIMER SYSCONFIG register takes 3 interface clock cycles and 3 functional
      clock cycles. If the DMTIMER is using the slow 32kHz functional clock this can
      take ~100us.
      
      Furthermore, during boot on an OMAP4430 panda board, I see that there are 100
      calls to _idle_sysc(), however, only 3 out of the 100 calls actually write
      the SYSCONFIG register with a new value.
      
      Therefore, to avoid unnecessary writes to device SYSCONFIG registers when
      idling the device, only write the value if the value has changed. It should be
      safe to do this on idle as the context of the register will never be lost while
      the device is active.
      
      Verified that suspend, CORE off and retention states are working with this
      change on OMAP3430 Beagle board.
      Signed-off-by: NJon Hunter <jon-hunter@ti.com>
      [paul@pwsan.com: updated to apply]
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      127500cc
    • A
      ARM: OMAP: DRA7: Enable PM framework initializations · 7de516a6
      Ambresh K 提交于
      Initialise powerdomains, clockdomains, and hwmod frameworks.
      Signed-off-by: NAmbresh K <ambresh@ti.com>
      Signed-off-by: NRajendra Nayak <rnayak@ti.com>
      [paul@pwsan.com: updated to apply]
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      7de516a6
    • A
      ARM: OMAP: DRA7: hwmod: Create initial DRA7XX SoC data · 90020c7b
      Ambresh K 提交于
      Adding the hwmod data for DRA7XX platforms.
      Signed-off-by: NAmbresh K <ambresh@ti.com>
      Signed-off-by: NTero Kristo <t-kristo@ti.com>
      Signed-off-by: NRajendra Nayak <rnayak@ti.com>
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      90020c7b
    • R
      ARM: OMAP: DRA7: Reuse the omap44xx_restart and fix the device instance · 1d597b07
      Rajendra Nayak 提交于
      The omap44xx_restart used on omap4 and omap5 devices can be reused
      on dra7 devices as well. The device instance however is different
      across omap5 and dra7 as compared to omap4. So fix this for omap5
      as well as dra7.
      Signed-off-by: NRajendra Nayak <rnayak@ti.com>
      Signed-off-by: NR Sricharan <r.sricharan@ti.com>
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      1d597b07
    • R
      ARM: OMAP: DRA7: powerdomain: Handle missing vc/vp · 9a4e301d
      Rajendra Nayak 提交于
      DRA7 belongs to the omap4plus devices which reuse the omap4_pwrdm_operations
      ops for powerdomain control. DRA7 however has no VC/VP while all the
      earlier omap4plus devices did.
      
      So use the .pwrdm_has_voltdm() ops to pass this info on to the core.
      Signed-off-by: NRajendra Nayak <rnayak@ti.com>
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      9a4e301d
    • A
      ARM: OMAP: DRA7: powerdomain: Add DRA7XX data and update header · 97dd16b1
      Ambresh K 提交于
      Add the data file to describe all power domains inside the DRA7XX SoC.
      Signed-off-by: NAmbresh K <ambresh@ti.com>
      Signed-off-by: NTero Kristo <t-kristo@ti.com>
      Signed-off-by: NRajendra Nayak <rnayak@ti.com>
      [paul@pwsan.com: added generation notation to comments]
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      97dd16b1
    • A
      ARM: OMAP: DRA7: clockdomain: Add DRA7XX data and update header · 11fadcfa
      Ambresh K 提交于
      Add the data file to describe all clock domains inside the DRA7XX SoC
      Signed-off-by: NAmbresh K <ambresh@ti.com>
      Signed-off-by: NTero Kristo <t-kristo@ti.com>
      Signed-off-by: NRajendra Nayak <rnayak@ti.com>
      [paul@pwsan.com: added generation notation to comments]
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      11fadcfa
    • A
      ARM: OMAP: DRA7: PRCM: Add DRA7XX local MPU PRCM regsiters · a61ef470
      Ambresh K 提交于
      Add the PRCM MPU registers for DRA7XX platforms
      Signed-off-by: NAmbresh K <ambresh@ti.com>
      Signed-off-by: NTero Kristo <t-kristo@ti.com>
      Signed-off-by: NRajendra Nayak <rnayak@ti.com>
      [paul@pwsan.com: added generation notation to comments]
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      a61ef470
    • R
      ARM: OMAP: DRA7: CM: Add minimal regbit shifts · 4f92bab4
      Rajendra Nayak 提交于
      This header contains minimal regbits that are currently used in code.
      This header has traditionally been autogenerated on OMAP4+ devices but
      the autogenerated contents are largely (95%) unused and hence to reduce
      unsued data in the kernel this header has been cut down (from the autogen
      output) to whatever is currently needed. This is done by running a cleanup
      script on top of the existing autogen script.
      Signed-off-by: NRajendra Nayak <rnayak@ti.com>
      Signed-off-by: NAmbresh K <ambresh@ti.com>
      [paul@pwsan.com: added generation notation in the comments]
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      4f92bab4
    • A
      ARM: OMAP: DRA7: CM: Add DRA7XX register defines · 40ca6091
      Ambresh K 提交于
      Add the new defines for DRA7XX CM registers.
      Signed-off-by: NAmbresh K <ambresh@ti.com>
      Signed-off-by: NTero Kristo <t-kristo@ti.com>
      Signed-off-by: NRajendra Nayak <rnayak@ti.com>
      [paul@pwsan.com: added generation notation in comments]
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      40ca6091