1. 28 2月, 2012 1 次提交
  2. 27 2月, 2012 3 次提交
  3. 23 2月, 2012 1 次提交
  4. 17 2月, 2012 2 次提交
    • D
      drm: add some caps for userspace to discover more info for dumb KMS driver (v2) · 019d96cb
      Dave Airlie 提交于
      For the simple KMS driver case we need some more info about what the preferred
      depth and if a shadow framebuffer is preferred.
      
      I've only added this for intel/radeon which support the dumb ioctls so far.
      
      If you need something really fancy you should be writing a real X.org driver.
      
      v2: drop cursor information, just return an error from the cursor ioctls
      and we can make userspace fallback to sw cursor in that case, cursor
      info was getting too messy, best to start smaller.
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      019d96cb
    • D
      drm: move pci bus master enable into driver. · 466e69b8
      Dave Airlie 提交于
      The current enabling of bus mastering in the drm midlayer allows a large
      race condition under kexec. When a kexec'ed kernel re-enables bus mastering
      for the GPU, previously setup dma blocks may cause writes to random pieces
      of memory. On radeon the writeback mechanism can cause these sorts of issues.
      
      This patch doesn't fix the problem, but it moves the bus master enable under
      the individual drivers control so they can move enabling it until later in
      their load cycle and close the race.
      
      Fix for radeon kms driver will be in a follow-up patch.
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      466e69b8
  5. 16 2月, 2012 2 次提交
  6. 15 2月, 2012 5 次提交
    • C
      drm/i915/lvds: Always use the presence pin for LVDS on PCH · f3cfcba6
      Chris Wilson 提交于
      With the introduction of the PCH, we gained an LVDS presence pin but we
      continued to use the existing logic that asserted that LVDS was only
      supported on certain mobile chipsets. However, there are desktop
      IronLake systems with LVDS attached which we fail to detect. So for PCH,
      trust the LVDS presence pin and quirk all the lying manufacturers.
      Tested-by: NDaniel Woff <wolff.daniel@gmail.com>
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43171Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NEugeni Dodonov <eugeni.dodonov@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      f3cfcba6
    • C
      drm/i915: Record the position of the request upon error · ee4f42b1
      Chris Wilson 提交于
      So that we can tally the request against the command sequence in the
      ringbuffer, or merely jump to the interesting locations.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      ee4f42b1
    • C
      drm/i915: Record the in-flight requests at the time of a hang · 52d39a21
      Chris Wilson 提交于
      Being able to tally the list of outstanding requests with the sequence
      of commands in the ringbuffer is often useful evidence with respect to
      driver corruption.
      
      Note that since this is the umpteenth per-ring data structure to be added
      to the error state, I've coallesced the nearby loops (the ringbuffer and
      batchbuffer) into a single structure along with the list of requests.  A
      later task would be to refactor the ring register state into the same
      structure.
      
      v2: Fix pretty printing of requests so that they are parsed correctly by
      intel_error_decode and use the 0x%08x format for seqno for consistency
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      52d39a21
    • C
      drm/i915: Record the tail at each request and use it to estimate the head · a71d8d94
      Chris Wilson 提交于
      By recording the location of every request in the ringbuffer, we know
      that in order to retire the request the GPU must have finished reading
      it and so the GPU head is now beyond the tail of the request. We can
      therefore provide a conservative estimate of where the GPU is reading
      from in order to avoid having to read back the ring buffer registers
      when polling for space upon starting a new write into the ringbuffer.
      
      A secondary effect is that this allows us to convert
      intel_ring_buffer_wait() to use i915_wait_request() and so consolidate
      upon the single function to handle the complicated task of waiting upon
      the GPU. A necessary precaution is that we need to make that wait
      uninterruptible to match the existing conditions as all the callers of
      intel_ring_begin() have not been audited to handle ERESTARTSYS
      correctly.
      
      By using a conservative estimate for the head, and always processing all
      outstanding requests first, we prevent a race condition between using
      the estimate and direct reads of I915_RING_HEAD which could result in
      the value of the head going backwards, and the tail overflowing once
      again. We are also careful to mark any request that we skip over in
      order to free space in ring as consumed which provides a
      self-consistency check.
      
      Given sufficient abuse, such as a set of unthrottled GPU bound
      cairo-traces, avoiding the use of I915_RING_HEAD gives a 10-20% boost on
      Sandy Bridge (i5-2520m):
        firefox-paintball  18927ms -> 15646ms: 1.21x speedup
        firefox-fishtank   12563ms -> 11278ms: 1.11x speedup
      which is a mild consolation for the performance those traces achieved from
      exploiting the buggy autoreported head.
      
      v2: Add a few more comments and make request->tail a conservative
      estimate as suggested by Daniel Vetter.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      [danvet: resolve conflicts with retirement defering and the lack of
      the autoreport head removal (that will go in through -fixes).]
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      a71d8d94
    • P
      drm/i915: add missing SDVO bits for interlaced modes on ILK · 7c26e5c6
      Paulo Zanoni 提交于
      This was pointed by Jesse Barnes. The code now seems to follow the
      specification but I don't have an SDVO device to really test this.
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      7c26e5c6
  7. 14 2月, 2012 4 次提交
    • D
      Merge tag 'drm-intel-next-2012-02-07' of... · cdbe8b54
      Dave Airlie 提交于
      Merge tag 'drm-intel-next-2012-02-07' of git://people.freedesktop.org/~danvet/drm-intel into drm-core-next
      
      * tag 'drm-intel-next-2012-02-07' of git://people.freedesktop.org/~danvet/drm-intel: (29 commits)
        drm/i915: Handle unmappable buffers during error state capture
        drm/i915: rewrite shmem_pread_slow to use copy_to_user
        drm/i915: rewrite shmem_pwrite_slow to use copy_from_user
        drm/i915: fall through pwrite_gtt_slow to the shmem slow path
        drm/i915: add debugfs file for swizzling information
        drm/i915: fix swizzle detection for gen3
        drm/i915: Remove the upper limit on the bo size for mapping into the CPU domain
        drm/i915: add per-ring fault reg to error_state
        drm/i915: reject GTT domain in relocations
        drm/i915: remove the i915_batchbuffer_info debugfs file
        drm/i915: capture error_state also for stuck rings
        drm/i915: refactor debugfs create functions
        drm/i915: refactor debugfs open function
        drm/i915: don't trash the gtt when running out of fences
        drm/i915: Separate fence pin counting from normal bind pin counting
        drm/i915/ringbuffer: kill snb blt workaround
        drm/i915: collect more per ring error state
        drm/i915: refactor ring error state capture to use arrays
        drm/i915: switch ring->id to be a real id
        drm/i915: set AUD_CONFIG N_value_index for DisplayPort
        ...
      cdbe8b54
    • Y
      drm/i915: Fix race condition in accessing GMBUS · 8a8ed1f5
      Yufeng Shen 提交于
      GMBUS has several ports and each has it's own corresponding
      I2C adpater. When multiple I2C adapters call gmbus_xfer() at
      the same time there is a race condition in using the underlying
      GMBUS controller. Fixing this by adding a mutex lock when calling
      gmbus_xfer().
      
      v2: Moved gmbus_mutex below intel_gmbus and added comments.
      Rebased to drm-intel-next-queued.
      Signed-off-by: NYufeng Shen <miletus@chromium.org>
      [danvet: Shortened the gmbus_mutex comment a bit and add the patch
      revision comment to the commit message.]
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      8a8ed1f5
    • W
      drm/i915: add a "force-dvi" HDMI audio mode · b1d7e4b4
      Wu Fengguang 提交于
      When HDMI-DVI converter is used, it's not only necessary to turn off
      audio, but also to disable HDMI_MODE_SELECT and video infoframe. Since
      the DVI mode is mainly tied to audio functionality from end user POV,
      add a new "force-dvi" audio mode:
      
      	xrandr --output HDMI1 --set audio force-dvi
      
      Note that most users won't need to set this and happily rely on the EDID
      based DVI auto detection.
      Reported-by: NAndrea Arcangeli <aarcange@redhat.com>
      Signed-off-by: NWu Fengguang <fengguang.wu@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      b1d7e4b4
    • S
      drm/i915: Don't lock panel registers when downclocking · 8ac5a6d5
      Sean Paul 提交于
      This patch replaces the locking from the downclock routines with an assert
      to ensure the registers are indeed unlocked. Without this patch, pre-SNB
      devices would lock the registers when downclocking which would cause a
      WARNING on suspend/resume with downclocking enabled.
      
      Note: To hit this bug, you need to have lvds downclocking enabled.
      Signed-off-by: NSean Paul <seanpaul@chromium.org>
      Acked-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      8ac5a6d5
  8. 13 2月, 2012 18 次提交
  9. 12 2月, 2012 3 次提交
  10. 11 2月, 2012 1 次提交